MIPP TDC Card Wu Jinyuan Fermilab PPDEED Apr

MIPP TDC Card Wu, Jinyuan Fermilab, PPD/EED Apr. 2007

The TDC Card • 96 Channels. • 12 connectors, 8 ch each. • Each MIPP_TDC FPGA digitize 48 channels inputs. • The MIPP_DCC FPGA concentrate data from two TDC FPGA devices. • Up to 32 K event/spill are stored in the SDRAM. • TDC resolution: 1. 18 ns (LSB). Bench tested @ 0. 69 ns (LSB) (See next pages) MIPP_TDC FPGA SDRAM MIPP_DCC FPGA RJ-45 MIPP_TDC FPGA

Clock Multiple Domain Sampling Changing TDC Inside FPGA • Sampling rate: 360 MHz x 4 phases = 1. 44 GHz. • LSB = 0. 69 ns. • Logic elements with critical timing are assigned as shown. c 0 QF Q 3 QE Q 2 QD Q 1 c 0 c 90 c 180 Q 0 c 270 4 Ch c 90 Trans. Detection & Encode Coarse Time Counter Logic elements with non-critical timing are freely placed by the fitter of the compiler. DV T 0 T 1 TS

Bench Test of TDC FPGA RAM Flash RAM e. Z 80 TDC 45 MHz Micro-processor address line driven by 45 MHz clock. 32 TDC bin = 1 clock cycle (0. 69 ns LSB) FPGA RAM Flash RAM TDC e. Z 80 45 MHz Micro-processor data line. Data out from different sources.

The FPGA TDC Test Card Shown here is Fermilab Beam Loss Monitor (BLM) Control Card VME Interface (As hit input) FPGA Serial Port Microprocessor

Differential Nonlinearity FPGA Quasi-random Input The “beat” between input and 45 MHz. TDC 45 MHz The placement above gives even bin width. Occupancy for each bin should 25%. The residual DNL < 690*(26 -22)/25 = 110 ps

TDC Data Concentration Substituting Multiple Error Sources with Single Error Source

TDC With Hit Rate Limiter 0 1 2 Reset 3 4 5 6 7 8 9 a b 1. 2 us Counter CC[5. . 2] T 1 TDC T 0 TDC/HRL DV DVLD CLR CK 212 LD CLRCNT Hit Rate Limiter CLRHIT (4/256 CK 212) 4 hits/256 CK 212, 4 hits/1. 2 ms 3. 3 MHz L/S TDC/HRL LD TDC/HRL c

TDC Data Concentration 96 Ch TDC/HRL Zero Supp. L 1 Buffer 1 x. M 4 K 16 x 256 Ch 4 -7, TDC & L 1 Buffer SDRAM 16 x 8 M/spill 16 MB/spill Ch 8 -11, TDC & L 1 Buffer Ch 12 -15, TDC & L 1 Buffer TDC/L 1 Buffer/MUX Channels 16 -31 EV Buffer & Truncating 16 x 128 x 2 TDC/L 1 Buffer/MUX Channels 32 -47 FPGA (DCC) EV Buffer & Truncating 16 x 128 x 2

Readout Timing 1. 2 us WR 0 1 2 3 4 5 6. 6 us G 0 B=0 G 0 B=1 G 4 B=0 G 4 B=1 G 8 B=0 G 8 B=1 6 RD G 12 B=0 7 8 9 0, 1 a b G 12 B=1 G 16 B=0 G 16 B=1 G 20 B=0 G 20 B=1 G 24 B=0 G 24 B=1 G 28 B=0 G 28 B=1 G 32 B=0 1. 2 us c G 32 B=1 G 44 B=1

Data Format 17 16 15 14 13 12 11 10 9 0 1 1 0 0 1 0 1 1 1 7 6 5 4 3 0 EHID[5. . 0] CNT[7. . 0] EV[13. . 0]=1, 2, . . 16 K-1 0 TS[7. . 0] CC[10. . 2] 0 0 1 1 2 1 0 0 P P BD_CHGRP[4. . 0] P CH[3. . 0] 0 1 8 Reserved Header/Ender T 1 T 0 P No Data EV Header 0 EV Header 1 CHGRP Header Hit Data Ender

Data Block No Data EV Header 0 EV Header 1 CHGRP Header CHGRP=0 No Data EV Header 0 EV Header 1 CHGRP Header CHGRP=3 Hit Data CHGRP Header CHGRP=1 CHGRP Header CHGRP=2 Hit Data Ender (=No Data) Hit Data CHGRP Header CHGRP=4 CHGRP Header CHGRP=5 Ender (=No Data) EV Header 1 CHGRP Header CHGRP=0 Hit Data CHGRP Header CHGRP=1 CHGRP Header CHGRP=2 Hit Data CHGRP Header CHGRP=3 Hit Data CHGRP Header CHGRP=4 CHGRP Header CHGRP=5 Ender (=No Data)

Useful Numbers: for 96 Channel Board RF 53. 102 MHz, 18. 8 ns CK 212. 4 MHz, 4. 708 ns LSB 1. 18 ns Hit Rate Limiter Setting 4 hits/256 CK 212 Double Hit Min. Separation 4 x. CK 106, 37. 7 ns Event Window 2 x 1. 2 ms Absolute Maximum Hits/event/48 ch 123 hits+5 header/trailers Event Maximum Size/96 ch 256 x 2 Bytes SDRAM port data rate 53 MHz x 2 Bytes Number of events/spill <32 K Absolute Maximum data/spill/FE card 8 M words Absolute Maximum data/spill/8 FE 4 hits/64 RF 128 x 2 Bytes 4. 8 ms/event 16 MB 128 MB Readout Chain Data Rate 26. 5 Mbits/s Absolute Maximum Spill Readout Time 48. 3 sec 4 hits/1. 2 ms, 3. 3 MHz 1280 Mbits

TDC Description • • The TDC FE card has three FPGA devices: two named MIPP_TDC and one named MIPP_DCC. Each MIPP_TDC digitizes 48 channels of inputs and sends data to MIPP_DCC which interfaces with a 16 MB SDRAM and the daisy -chained interface to ship data back to the controller. A TDC_FE card supports 96 input channels. Each channel in the MIPP_TDC has a hit limiter. The time is split into 1. 2 us (or 64 RF, RF=1/53 MHz) periods which are counted after the reset at the start of each spill. In each of the 1. 2 us, the number of hits in each channel is limited to 4 hits. A channel group contains 4 channels. Every 4 cycles of CK 106 (106 MHz), hit data in each channel is written to the hold-shift register. The hold-shift register then shift data of the 4 channels, one in each CK 106 cycle, to the zero suppression block. Therefore, the hit separation in each channel is 4 x 1/106 MHz = 37. 7 ns. The zero-suppressed data from the 4 -channel groups, i. e. , only the valid hits are stored in the L 1 pipeline buffers. A pipeline buffer is organized as 16 blocks of 16 words with 16 -bit/word which uses a M 4 K RAM. Each hit is stored as a 16 -bit word, each channel can have maximum 4 hits in 1. 2 us. Therefore, a 16 words block holds data of 4 channels in 1. 2 us. The entire L 1 pipeline length is 16 x 1. 2 us = 19. 3 us. Up to about 18 us trigger latency are supported. For each trigger, data in 2 x 1. 2 us time window are readout, which corresponding to 2 16 -word blocks in the L 1 pipeline buffer. Data from 16 channels are grouped together, taking 1. 2 us to transfer from the L 1 pipeline buffer to the EV buffer. Data of 48 channels are transferred in 3. 6 us. Truncating happens while storing data into EV buffer if too many channels are hot. The data for an event stored in the EV buffer contains 2 headers and 3 enders, one at the end of each 16 -channel group. The total number of hits allowed in 48 channels is 123. The truncated data block is not good for experiment data, however, it contains all necessary header and enders to avoid hanging up the remaining readout system. Up to 256 16 -bit words/event for 96 channels are stored in the 16 MB SDRAM. A total of 32 K events can be held in the SDRAM. Daisy chained 8 TDC_FE cards are readout through a 26. 5 Mbit/s data link to the controller. The total time to readout 8 x 16 MB is about 48. 3 sec.

FPGA AMP & Shaper ADC ADC Using FPGA • Analog signals from AMP & Shapers are directly fed to FPGA pins. • FPGA output and passive RC network are used to generate ramping reference voltage VREF. • The input voltages and VREF are compared using FPGA differential input receiers. • The times of transitions representing input voltage values are digitized by TDC blocks in FPGA AMP & Shaper TDC V 1 VREF R 1 V 2 R 1 C R 2 T 1 T 2 V 3 T 3 V 4 T 4

ADC Test: Reference on BD 3_19 FPGA TDC VREF 50 50 1000 p. F t = 59 ns 100 • Longer time constant causes the V-T curve to be nearly linear. • Sampling rate: 22. 5 MHz (2/88 ns). • Measurement range: 6 bits. • Sensitivity: 10 m. V/LSB.

ADC Test: Waveform Digitization on BD 3_19 Input Waveform Converted Raw Data Input Waveform, Overlap Trigger

ADC Test: Reference on BD 4_22 FPGA TDC VREF 50 50 150 p. F t = 7. 5 ns 100 • Shorter time constant causes the V-T curve to be exponential. • Sampling rate: 22. 5 MHz (2/88 ns). • Measurement range: 6 bits. • Sensitivity < 6 m. V/LSB. • Dynamic Range: ~8 bits.

ADC Test: Waveform Digitization on BD 4_22 Raw Data Small pulses are emphasized by the trailing ramp measurement. Input Waveform Converted The data measured by trailing ramp is much more smoother than the leading ramp for small pulses.

ADC Test: Summary Time Constant Ramping Time & Sampling Rate Sensitivity Full Scale Range Measurement & Dynamic Range BD 4 146 ns Discharge 353 ns > 2 MHz 1. 1 m. V /LSB (@ 0. 3 V) . 25 -2. 7 V 9 bits & ~12 bits BD 3_19 59 ns 44 ns 22. 5 MHz 10 m. V /LSB 1. 4 -2. 05 V 6 bits BD 4_22 7. 5 ns 44 ns 22. 5 MHz <6 m. V /LSB (@1. 02 V) 1. 02 -2. 48 V 6 bits & ~8 bits

Notes • Like in any analog circuits, noise reduction is the key to reach good resolution. Two primary measures are taken: – Appropriate arrangement of the grounding for analog signals. – Microprocessor are put in “wait” state during ramping and comparing. • Large noise due to single ended TTL are bad. But small and random noise from differential outputs can be good for “dithering”. This is to be studied. • Being non-linear, the RC exponential charging curve is bad. But it allows expansion of dynamic range, which is good. The conversion to linear scale in FPGA is very simple.

Remarks • The ADC functions tested have met requirements of many applications in high energy physics and accelerator instrumentation. • The FPGA ADC will not completely replace commercial ADC or ASIC. But it is appealing for sake of convenience (like for slow control/monitoring) or for low cost with large channel count (like for straw tube or TPC chambers).