MIPI CSI DPHY Tx SOF EOF after hsync

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MIPI CSI, D-PHY Tx SOF, EOF after hsync change to assert low during vsync

MIPI CSI, D-PHY Tx SOF, EOF after hsync change to assert low during vsync asserted high B. Magid 25 -Jun-18

Overview zoomed out

Overview zoomed out

Zoomed in further around vsync

Zoomed in further around vsync

Examine Potential EOF just before Vertical Blanking

Examine Potential EOF just before Vertical Blanking

Zoom in before VSYNC goes high on what may be LP-11, LP-00 (part of

Zoom in before VSYNC goes high on what may be LP-11, LP-00 (part of SOT of short packet for EOF? ? ? – see next slide where I’ve expanded the LP busses

Expanded hs_p, hs_n, lp_p, lp_n busses for 4 MIPI lanes and zoomed in. Yellow

Expanded hs_p, hs_n, lp_p, lp_n busses for 4 MIPI lanes and zoomed in. Yellow cursor in same location as previous photo LP 11 ->LP 00 HS sync sequence “ 00011101”? ? (see next slide)

Zoom in on potential HS sync sequence “ 00011101” between 2 yellow cursors ASSUMING

Zoom in on potential HS sync sequence “ 00011101” between 2 yellow cursors ASSUMING 0 transmitted 1 st After this “ 00011101” things don’t make sense because I thought this was the end of the So. T and would next see a Data ID of 0 x 00 for SOF and I don’t see 8 zeros. Is this correct?

Zoom out a bit – didn’t see another instance of the “ 00011101” pattern

Zoom out a bit – didn’t see another instance of the “ 00011101” pattern between the blue and yellow cursor – just the on the previous page which didn’t make sense and looked identical to what it had been before the hsync change.

Examine Potential SOF just after Vertical Blanking

Examine Potential SOF just after Vertical Blanking

Zoom in when vertical sync/blanking ends – Yellow cursor shows potential LP 11, LP

Zoom in when vertical sync/blanking ends – Yellow cursor shows potential LP 11, LP 00 SOT Getting a “glitch” on hsync- it’s 1 AXI_CLK wide - Could this be a problem? (see next slide)

Zoom in glitch on hsync seems to be because vsync deasserts low a clock

Zoom in glitch on hsync seems to be because vsync deasserts low a clock before hsync would assert low

Expanded hs_p, hs_n, lp_p, lp_n busses to shows the 4 MIPI lanes (into the

Expanded hs_p, hs_n, lp_p, lp_n busses to shows the 4 MIPI lanes (into the D-phy)

Zoom in further – cursor in same place as previous slide LP 11 ->LP

Zoom in further – cursor in same place as previous slide LP 11 ->LP 00 HS sync sequence “ 00011101”? ? (see next slide)

Zoom in on potential HS sync sequence “ 00011101” between 2 yellow cursors ASSUMING

Zoom in on potential HS sync sequence “ 00011101” between 2 yellow cursors ASSUMING 0 transmitted 1 st After this “ 00011101” things don’t make sense because I thought this was the end of the So. T and would next see a Data ID of 0 x 01 for EOF but that doesn’t seem to happen. Is this correct? - Looks like it did before hsync change vertically

Zoom in on another potential HS sync sequence “ 00011101” (only on hs_p[3]) between

Zoom in on another potential HS sync sequence “ 00011101” (only on hs_p[3]) between 2 yellow cursors ASSUMING 0 transmitted 1 st – still don’t see ID of 0 x 01 for EOF