MIMOSA 22 MIMOSA 26 ULTIMATE Christine HUGUO IPHCStrasbourg

MIMOSA 22 MIMOSA 26 ULTIMATE Christine HU-GUO (IPHC-Strasbourg)

MIMOSA 22 n AMS-OPTO 0. 35µm Dim. pixel 18. 4 x 18. 4 µm² Dim. Matrice 136 x 576 pixels Ä 8 sorties analogiques Ä 128 sorties numériques Vitesse d’intégration < 100µs Slow Control : JTAG Références internes (DAC) Lecture multiplexée 50 MHz n Non inclus: suppression de zéros n Soumission : octobre 2007 Retour de fonderie : janvier 2008 n n n n 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 2

In Pixel amplification & Signal Processing (1) 16 pix Slct_Row Slct_Gr Slct_Row Integrated in Discri. 16 pix Slct_Row Slct_Gr Slct_Row n 4 digital control signals per row: PWR_On, Slct_Row, Slct_Grp, Clamping Ä Ä 15 -17/06/2009 Slct_Row (16 x. CK), PWR_On (2 x 16 x. CK), Slct_Gr (16 x 16 x. CK): power activate signals Clp: signal for CDS (3 x. CK) STAR meeting IPHC christine. hu@ires. in 2 p 3. fr RD CALIB LATCH Column –level discriminator 3

In Pixel amplification & Signal Processing (2) n Common Source (CS) amplification in pixel Ä Only NMOS transistors can be used 1 2 CS + Reset bias reset Nwell / Pepi reset M 3 out M 1 signal current M 2 M 4 Improved CS + Feedback + Self biased Low-pass filter M 3 signal current M 2 M 4 M 5 M 3 feedback out M 1 Nwell / Pepi 3 Improved CS + Reset Pdiff / Nwell / Pepi M 2 signal current a negative low frequency feedback was introduced to decrease amplification gain variations due to process variations 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 4

In Pixel amplification & Signal Processing (3) n Measured Mimosa 22 pixel (Amp+CDS) performances (20 °C) before irradiation: Pixel types CS + Reset 1 Improved CS + Reset 2 Improved CS + Feedback + self biased 3 n Diode size (µm 2) CVF* (µV/e-) ENC (e-) 15. 21 57. 3 13. 3 +/- 0. 1 15. 21 57. 3 13. 0 +/- 0. 1 14. 62 55. 8 12. 3 +/- 0. 1 After ionizing irradiation, feedback self-biased structure performances (conditions: +20 C, integration time ~92μs) has the best 3 ¨ 3 1 ¡ 2 2 1 ¶ 3 1 BUT from previous studies (MIMOS 15) on chips without in-pixel signal processing the noise was in order of ~15 e after dose of 1 MRad 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 5

Increasing Radiation Tolerance in Pixel n Ionizing radiation tolerance (22 bis, 22 ter): Ä Pixel circuit level: n Ä ELT for the transistor connected to the detection diode Diode level: n Remove thick oxide surrounding N-well diode by replacing with thin-oxide Low-pass filter M 4 M 5 feedback Pdiff / Nwell / Pepi M 3 M 2 signal current n n Non-ionizing radiation tolerance: Reducing pixel pitch < 20 µm 18. 4 µm Ä Increasing sensing diode size: limited by layout Ä Reducing integration time ~100 -200 µs Ä 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 6

Column-level discriminators n Discriminator design considerations: Ä Ä Small input signal Offset compensated amplifier stage Dim: 16. 4 x 430 µm 2 Conversion time = row read out time (~200 ns) Consumption ~230 µW Vclp_d REF 1 RD RD RD REF 2 Q CALIB LATCH To Pixel RD Q RD CALIB Vclp_d LATCH RD Column-level Double Sampling (DS) reduce pixel to pixel dispersion (FPN) 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 7

Column-level discriminators: characterizations Analyze Method Scan threshold voltage (N discri. ) Ä Fit to an error function Ä Mean Offset Ä Sigma temporal noise (TN) Ä n n Mean of N sigma average of TN RMS of N offsets FPN Resultants FPN : 0. 2 m. V Ä TN : 0. 3 m. V Ä 15 -17/06/2009 0. 3 m. V STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 0. 2 m. V 8

Mimosa 22 test results: Pixels + 128 Discriminators n Test in lab: n Ä Temporal Noise: Ä FPN: Beam test with 120 Ge. V pions at CERN-SPS 0. 64 m. V 11. 5 e 0. 22 m. V 3. 9 e- 0. 64 m. V Ä Threshold ~ 4 m. V 6 σ noise 0. 22 m. V n n n 15 -17/06/2009 STAR meeting Detection efficiency > 99. 5% Spatial resolution < 4 µm Fake rate < 10 -4 IPHC christine. hu@ires. in 2 p 3. fr 9

MIMOSA 26: 1 st Sensor with Integrated Ø Chip size : 13. 8 x 21. 6 mm 2, AMS C 35 B 4: 0. 35µm technology n Testability: several test points implemented all along readout path n Pixels out (analogue) n Discriminators n Zero suppression n transmission n n n Pixel array: 576 x 1152, pitch: 18. 4 µm Active area: ~10. 6 x 21. 2 mm 2 In each pixel: Ø Amplification Ø CDS (Correlated Double Sampling) Row sequencer Width: ~350 µm 1152 column-level discriminators Ø offset compensated high gain preamplifier followed by latch n Zero suppression logic n Reference Voltages Buffering for 1152 discriminators n I/O Pads Power supply Pads Circuit control Pads LVDS Tx & Rx 15 -17/06/2009 n n Current Ref. Bias DACs STAR meeting n n Readout controller JTAG controller n n Memory management Memory IP blocks IPHC christine. hu@ires. in 2 p 3. fr n Test blocks PLL, 8 b/10 b 10

Readout Chain: Pixel + discriminator RD Vclp_d REF 1 RD REF 2 RD Q CALIB LATCH To Pixel RD Q RD CALIB n Need to drive ~2 cm long line Ä Even an ideal voltage source CANNOT satisfy these requirements 1152 discriminators are divided into 4 groups, 4 bias DAC Ø RC distribution line + successive charge rejections compensate process dispersions of discriminators DAC STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 288 discriminators DAC 288 discriminators REF 288 discriminators DAC 288 discriminators discriminator Ex. RD (3 CK ~ 30 ns) Ä n discriminator LATCH Need stable signals during "RD" & "CALIB" periods n discriminator RD Reference voltages (threshold) & clamping voltage are analogue signals which have to apply to 1152 discriminators Ä 1152 discriminators 15 -17/06/2009 Vclp_d 11

………… A/D Column 0 n Connected to column-level discriminators outputs Zero suppression is based on row by row sparse data scan readout and organized in pipeline mode in three steps: ………… A/D Discriminators Pixel Array n Column 1152 Readout Chain: zero suppression + memories Core of the zero suppression Sparse Data Scan (N states) ………… Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 12

Readout Chain: zero suppression + memories 1 st step: Ø ………… A/D Ø 1152 columns terminations 18 banks // scan Based on a sparse data scan algorithm to find hit pixels (discriminator output = "1") Ä Up to 4 contiguous pixel signals above Vth will be encoded in a 2 bits state word following by address of the 1 st pixel Find up to N states with column addresses per bank Column 1152 Column 0 Ø A/D n Core of the zero suppression Sparse Data Scan (N states) ………… Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 13

……. … Readout Chain: zero suppression + memories state Row M+1 state ……. . …. … Row M-1 HIT State Row M 0 0 1 1 0 0 0 State 1 0 0 0 1 1 1 0 0 State 2 Binary code 1 0 00 1 1 0 0 01 1 0 10 1 1 11 2 bits binary code Column address of the 1 st pixel State: Column address of the 1 st pixel+ 2 bits code 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 14

2 nd step: n ………… Read out the outcomes of the 1 st step in all banks and keep up to M states Add row and bank addresses ………… A/D n A/D Column 0 n Column 1152 Readout Chain: zero suppression + memories Core of the zero suppression Sparse Data Scan (N states) ………… Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 15

Readout Chain: zero suppression + memories Ø Ø nd ………… The memory is made of 2 IP's buffers continuous read-out S 0 S 17 Ä 1 buffer stores current frame, 1 buffer is read out previous frame Serial transmission by LVDS pad ………… Column 1152 Column 63 Ø Store the outcomes of the 2 step to a memory ………… Column 0 ………… Column 63 Column 0 3 rd step: A/D n Column 63 Column 0 N, M, Memory capacity and Memory Read-out speed depend on hit density N = 6, M = 9, Memory ~ 40 Kbits, Nominal Read-out Freq. : 80 MHz Core of the zero suppression Sparse Data Scan (N states) ………… Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 16

Test MIMOSA 26 n n n Mimosa 26 returned from foundry on February 2009. Extensive tests are going on in the laboratory. Measured temporal noise = 0. 6 -0. 7 m. V and FPN = 0. 3 -0. 4 m. V for pixel array with its associated discriminators. Ä These values are equivalent to those obtained with Mimosa 22. Ä Figures show measured results for one quarter of the matrix with column-level discriminators. The remaining three quarters of the matrix exhibit similar performances showing a good uniformity of the whole 576 x 1152 pixels with the 1152 discriminators n The characterization of Mimosa 26 will be completed by the beam tests planned in Summer 2009 + yield evaluation 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 17

MIMOSA 26 ULTIMATE n Zero suppression: physics condition : 2, 4 x 105 hits/s/cm 2 Ä n Readout time 200 µs ~ 200 hits/frame/sensor The highest luminosity expected at STAR for RHIC 2 gives: 60 hits / cm 2 , s = 8 hits Ä On the inner layer of sensors in a 200 µs integration window. Ä This rate is for interactions and peripheral collisions. Possible background sources are not included. Ä ~450 hits /sensor Ä n 450 hits + 240 Noisy pixels ¨ n > 5 s & ~2 x 10 -4 noisy pixels 530 hits /frame equivalent Safety factor ? 1. SUZE design: Ä Ä 2. Maximum output speed: ~100 Mbits/s 2 memories of (200 x 3) x 32 bits With new condition & with ~ 10 -4 ~ 100 noisy pixels Ä Ä Zero suppression based on SUZE's group & row hits finders design Points have to be changed: 1. 2. 3. 15 -17/06/2009 Increase maximum output speed: up to 256 Mbits/s Increase dimension of memory: > 3 times larger (2048 x 32)x 2 Memory: anti latch up? STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 18

Power Consumption 500 hits Pixel Pitch 18. 4 µ Pixel Discri. DAC Group Hits Finder Line Hits Finder Sq. controller 230 m. W 0. 2 x 1152 350 m. W 0. 3 x 1152 20 m. W 60 m. W 15 m. W x 4 6 m. W 20 m. W 15 -17/06/2009 STAR meeting Memory 34 m. W IPHC christine. hu@ires. in 2 p 3. fr LVDS receiv. 8 m. W LVDS trans. 66 m. W (16. 5 x 4) Total (m. W) 794 Power (m. W/cm 2) 172 19

Frequency distribution n Circuit needs: Ä CK : Ä Pixels & Comparators: Ä SUZE CK: Ä LVDS out: n 80 MHz 16 CK 5 MHz 80 MHz 2 x 120 MHz 2 x 160 MHz Input Freq. : Ä 160 MHz external CK Ä Option: 80 MHz external CK Ä Option: 10 MHz external CK, PLL (N=16) output Freq. : 160 MHz n n 80 MHz will be made in chip Possibility to integrate 8 b/10 b encoding to allow reasonable clock recovery Ä Option for the Ultimate 1 chip Pixels & Comparators 8 b/10 b 16 MHz 80 MHz ÷ 10 ÷ 2 160 MHz LVDS PLL (N=16) LVDS 10 MHz 160 MHz 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 20

Ultimate Sensor Testing Functionality (implemented in MIMOSA 26) Analogue pixels outputs Pixel Array switch Inject 2 Test Voltages to emulate pixels outputs comparators switch Read One Row Register, Pixels & Comparators are in normal mode, tint = 200µs, Readout freq. = 5 MHz via 2 LVDS output pads. The auto increment functional logic to scan whole matrix will be studied. switch Inject 2 SUZE Test Rows SUZE 160 MHz switch Inject Test Pattern of 32 bits to emulate memory outputs 5 MHz 160 MHz MUX LVDS 15 -17/06/2009 MUX CK LVDS MUX Data LVDS STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 21

Latch-up 15 -17/06/2009 STAR meeting IPHC christine. hu@ires. in 2 p 3. fr 22