MICROPROCESSORS AND MICROCONTROLLERS 17 CS 44 SIGNED NUMBERS

MICROPROCESSORS AND MICROCONTROLLERS 17 CS 44 SIGNED NUMBERS AND STRINGS, MEMORY AND MEMORY INTERFACING, 8255 I/O PROGRAMMING Module-3 Mrs. Deep Yogish Asst. Professor Dept. of CSE KSSEM, Bengaluru-109 1

BOOKS REFERRED Muhammad Ali Mazidi, Janice Gillispie Mazidi, Danny Causey, The x 86 PC Assembly Language Design and Interfacing, 5 th Edition, Pearson, 2013. Barry B Brey, The Intel Microprocessors, 8 th Edition, Pearson Education, 2009. 2

OBJECTIVES Convert a number to its 2’s complement. Code signed arithmetic instructions: § ADD, SUB, IMUL, and IDIV. Demonstrate how arithmetic instructions affect the sign flag. Explain the difference between a carry and an overflow. Prevent overflow errors by sign-extending data. Code signed shift instructions: § SAL and SAR. 3

OBJECTIVES Code logic instruction CMP for signed numbers and explain its effect on the flag register. Code conditional jump instructions after CMP of signed data. Explain the function of registers SI and DI in string instructions. Describe the operation of the direction flag in string instructions. Code instructions CLD and STD to control the direction flag. 4

OBJECTIVES Describe the operation of the REP prefix Code string instructions: § § § MOVSB and MOVSW for data transfer. STOS, LODS to store and load the contents of AX. CMPS to compare two strings of data. SCAS to scan a string for data matching in AX. XLAT for table processing. 5

SIGNED NUMBERS AND STRINGS 6

SIGNED NUMBER ARITHMETIC OPERATIONS Concept of signed numbers in computers Many applications require signed data, & computers must be able to accommodate such numbers. § The most significant bit (MSB) is set aside for the sign (+ or -) & the rest of the bits are used for the magnitude. § The sign is represented by 0 for positive (+) numbers and 1 for negative (-) numbers. 7

SIGNED NUMBER ARITHMETIC OPERATIONS Signed byte operands In signed byte operands, D 7 (MSB) is the sign and D 0 to D 6 are set aside for the magnitude of the number. § If D 7 = 0, the operand is positive. § If D 7 = 1, it is negative. 8

SIGNED NUMBER ARITHMETIC OPERATIONS Positive numbers The range of positive numbers that can be represented by the format above is 0 to +127. § If a positive number is larger than +127, a word-sized operand must be used. 9

SIGNED NUMBER ARITHMETIC OPERATIONS Negative numbers For negative numbers D 7 is 1, but the magnitude is represented in 2's complement. 10

SIGNED NUMBER ARITHMETIC OPERATIONS Negative numbers 11

SIGNED NUMBER ARITHMETIC OPERATIONS Byte-sized signed number ranges. 12

SIGNED NUMBER ARITHMETIC OPERATIONS Word-sized signed numbers A word is 16 bits in length in x 86 computers. § Setting aside the MSB (D 15) for the sign leaves a total of 15 bits (D 14 – D 0) for the magnitude. § A range of -32768 to +32767. Larger numbers is must be treated as a multiword operand, processed chunk by chunk. § The same way as unsigned numbers. 13

SIGNED NUMBER ARITHMETIC OPERATIONS The range of signed word operands. 14

SIGNED NUMBER ARITHMETIC OPERATIONS To convert a negative number to its word operand representation, the same three steps discussed in negative byte operands are used: 15

SIGNED NUMBER ARITHMETIC OPERATIONS Signed number operations overflow problem When using signed numbers, a serious issue, the overflow problem, must be dealt with. § The CPU understands only 0 s & 1 s, ignoring the human convention of positive/negative numbers. § The CPU indicates the problem with the OF (overflow) flag. If the result of an operation on signed numbers is too large for the register, an overflow occurs. § Review Example next slide 16

SIGNED NUMBER ARITHMETIC OPERATIONS +96 is added to +70 and the result according to the CPU is 90. Why? The result was more than AL could handle, because like all other 8 -bit registers, AL could only contain up to +127. 17

SIGNED NUMBER ARITHMETIC OPERATIONS The overflow flag in 8 -bit operations In 8 -bit signed number operations, OF is set to 1 if: § There is a carry from D 6 to D 7 but no carry out of D 7. § (CF = 0) § There is a carry from D 7 out, but no carry from D 6 to D 7. § (CF = 1) The overflow flag is set to 1 if there is a carry from D 6 to D 7 or from D 7 out, but not both. § If there is a carry both from D 6 to D 7, and from D 7 out, then OF = 0. 18

SIGNED NUMBER ARITHMETIC OPERATIONS In Example 6 -4, since there is only a carry from D 6 to D 7 and no carry from D 7 out, OF = 1. § Examples 6 -5, 6 -6, and 6 -7 give further illustrations of the overflow flag in signed arithmetic. 19

SIGNED NUMBER ARITHMETIC OPERATIONS 20

SIGNED NUMBER ARITHMETIC OPERATIONS Overflow flag in 16 -bit operations In a 16 -bit operation, OF is set to 1 in two cases: § A carry from D 14 to D 15, but no carry out of D 15. § (CF = 0). § A carry from D 15 out but no carry from D 14 to D 15. § (CF = 1) Again, the overflow flag is low (not set) if there is a carry from both D 14 to D 15 and from D 15 out. § See examples in next slide. 21

SIGNED NUMBER ARITHMETIC OPERATIONS 22

SIGNED NUMBER ARITHMETIC OPERATIONS Avoiding erroneous results Sign-extending the operand can avoid problems associated with signed number operations. § This copies the sign bit (D 7) of the lower byte of a register into the upper bits of the register. § Or copies the sign bit of a 16 -bit register into another register. Two instructions are used to perform sign extension: § CBW (convert signed byte to signed word) § CWD (convert signed word to signed double word) 23

SIGNED NUMBER ARITHMETIC OPERATIONS CBW will copy D 7 (the sign flag) to all bits of AH. § The operand is assumed to be AL, and the previous contents of AH are destroyed. § OR 24

SIGNED NUMBER ARITHMETIC OPERATIONS CWD sign-extends AX, copying D 15 of AX to all bits of the DX register. § This is used for signed word operands. § Another example : 25

SIGNED NUMBER ARITHMETIC OPERATIONS Example 6 -10 shows 6 -4 rewritten to correct for overflow. § If the overflow flag is not raised, the result of the signed number is correct & JNO (jump if no overflow) will jump to OVER. 26

SIGNED NUMBER ARITHMETIC OPERATIONS Example 6 -10 shows 6 -4 rewritten to correct for overflow. § If OF = 1, result is erroneous & each operand must be sign extended, then added. This works for addition of any two signed bytes. 27

SIGNED NUMBER ARITHMETIC OPERATIONS Analysis of the values in Example 6 -10. § Each is sign-extended and added as follows: § If the possibility of overflow exists, byte-sized signed numbers should be sign-extended into a word, § Word-sized signed operands should be sign-extended before they are processed 28

SIGNED NUMBER ARITHMETIC OPERATIONS IDIV signed number division IDIV means "integer division”, used for signed number division. § All 8088/86 arithmetic instructions are for integer numbers, regardless of whether the operands are signed or unsigned. § Real numbers operations are done by the 8087 coprocessor. 29

SIGNED NUMBER ARITHMETIC OPERATIONS IMUL signed number multiplication Similar in operation to the unsigned multiplication. § Operands in signed number operations can be positive or negative, and the result must indicate the sign. 30

SIGNED NUMBER ARITHMETIC OPERATIONS Program to computes the average of temperatures: +13, -10, +19, +14, -18, -9, +12, -19, +16, Celsius. 31

SIGNED NUMBER ARITHMETIC OPERATIONS 32

SIGNED NUMBER ARITHMETIC OPERATIONS SAR/SAL SAR destination, count § As the bits of the destination are shifted to the right into CF, the empty bits are filled with the sign bit. 33

SIGNED NUMBER ARITHMETIC OPERATIONS SAL (shift arithmetic left) and SHL (shift left) do exactly the same thing. § Basically the same instruction with two mnemonics. § As far as signed numbers are concerned, there is no need for SAL. 34

SIGNED NUMBER ARITHMETIC OPERATIONS CMP signed number comparison CMP dest, source § The same for both signed and unsigned numbers. § The J condition instruction used to make a decision is different from that used for the unsigned numbers. In unsigned number comparisons CF and ZF are checked for conditions of larger, equal, and smaller. § In signed number comparison, OF, ZF, SF are checked. 35

SIGNED NUMBER ARITHMETIC OPERATIONS Mnemonics used to detect the conditions above: § Example 6 -12 on page 185 should help clarify how the condition flags are affected by the compare instruction. § Program 6 -2 on page 186 is an example of the application of the signed number comparison. § It uses the data in Program 6 -1, and finds the lowest temperature. 36

SIGNED NUMBER ARITHMETIC OPERATIONS 37

SIGNED NUMBER ARITHMETIC OPERATIONS FIND THE LOWEST TEMPERATURE 38

STRING AND TABLE OPERATIONS String instructions in the x 86 family are capable of operations on a series of operands located in consecutive memory locations. While CMP can compare only 2 bytes (or words) of data, CMPS (compare string) compares two arrays of data located in memory locations. § Pointed at by the SI and DI registers. 39

STRING AND TABLE OPERATIONS SI & DI, DS & ES in string instructions For string operations to work, CPU designers set aside certain registers for specific functions, to permanently provide source/destination operands. § In 8088/86 processors, SI & DI registers always point to the source and destination operands, respectively. To generate the physical address, 8088/86 always uses SI as the offset of the DS (data segment) register and DI as the offset of ES (extra segment). § The ES register must be initialized for the string operation to work. 40

STRING AND TABLE OPERATIONS SI Data Segment Source_Variable DI Extra Segment Dest_Variable 41

STRING AND TABLE OPERATIONS Byte/word operands in string instructions The operand can be a byte or a word, distinguished by letters B (byte) & W (word) in the mnemonic. 42

STRING AND TABLE OPERATIONS DF, the direction flag To process operands in consecutive locations requires the pointer to be incremented/decremented. § In string operations, achieved by the direction flag. § Flag register bit 11 (D 10) is set aside for the direction flag (DF). The programmer to specifies the choice of increment or decrement by setting the direction flag high or low. § CLD (clear direction flag) will reset (zeroes) DF, telling the string instruction to increment the pointers automatically. § Sometimes is referred to as autoincrement. § STD (set the direction flag) performs the opposite function. § Sets DF to 1, indicating that the pointers SI and DI should be decremented automatically. 43

STRING AND TABLE OPERATIONS SI SI SI DI DI Data Segment Source_Variable Extra Segment Dest_Variable 44

STRING AND TABLE OPERATIONS REP prefix The REP (repeat) prefix allows a string instruction to perform the operation repeatedly. § REP assumes that CX holds the number of times the instruction should be repeated. (until CX becomes zero) In Example 6 -13, after transfer of every byte by the MOVSB instruction, both the SI and DI registers are incremented automatically once only (notice CLD). § The REP prefix causes the CX counter to decrement, and MOVSB is repeated until CX becomes zero. § Both DS and ES are set to the same value. 45

STRING AND TABLE OPERATIONS 46

STRING AND TABLE OPERATIONS SI Data Segment DATA 1 DI Extra Segment DATA 2 47

STRING AND TABLE OPERATIONS An alternative solution would change only two lines of code: § MOVSW will transfer a word (2 bytes) at a time and increment SI & DI registers each twice. § REP will repeat that process until CX becomes zero. § CX has the value of 10 in it, as 10 words is equal to 20 bytes. 48

STRING AND TABLE OPERATIONS STOS instruction STOSB stores the byte in register AL into memory locations pointed at by ES: DI. § If DF = 0, then DI is incremented once. § If DF = 1, then DI is decremented. STOSW stores the contents of AX in ES: DI and ES: DI+1 (AL into ES: DI and AH into ES: DI+1) § If DF = 0, then DI is incremented twice. § If DF = 1, then DI is decremented twice 49

STRING AND TABLE OPERATIONS LODS instructions LODSB loads the contents of memory locations pointed at by DS: SI into AL. § Increments SI once, if DF = 0. § Decrements SI once, if DF = 1. LODSW loads the contents of memory locations pointed at by DS: SI into AL, and DS: SI+1 into AH. § SI is incremented twice if DF = 0, else it is decremented twice. LODS is never used with a REP prefix. 50

STRING AND TABLE OPERATIONS Testing memory using STOSB and LODSB Example 6 -14 on page 189 uses string instructions STOSB & LODSB to test an area of RAM memory. § First AAH is written into 100 locations by using word-sized operand AAAAH, and a count of 50. § In the test, LODSB brings the contents of memory locations into AL, one by one, and each is e. Xclusive-ORed with AAH. (register AH has hex value AA). § If they are the same, ZF = 1 and the process is continued. § Otherwise, the pattern written there by the previous routine is not there and the program will exit. 51

STRING AND TABLE OPERATIONS Write a program that: § (1) Uses STOSB to store byte AAH into 100 memory locations. § (2) Uses LODS to test the contents of each location to see if AAH was there. If the test fails, the system should display the message "bad memory". 52

STRING AND TABLE OPERATIONS 53

STRING AND TABLE OPERATIONS REPZ and REPNZ prefixes Used with CMPS & SCAS for testing purposes. § REPZ (repeat zero) - the same as REPE (repeat equal), will repeat the string operation as long as the source and destination operands are equal (ZF = 1) or until CX becomes zero. § REPNZ (repeat not zero) - the same as REPNE (repeat not equal), will repeat the string operation as long as the source and destination operands are not equal (ZF = 0) or until CX becomes zero. § CMPS (compare string) - allows the comparison of two arrays of data pointed at by registers SI & DI. § CMPS can test inequality of two arrays using "REPNE CMPSB". 54

STRING AND TABLE OPERATIONS SCASB (scan string) SCASB compares each byte of the array pointed at by ES: DI with the contents of the AL register. § Depending on which prefix, REPE or REPNE, is used, a decision is made for equality or inequality. In Example 6 -16, on page 191, the letter "G" is compared with "M". § Since they are not equal, DI increments, CX decrements § Scanning is repeated until letter "G" is found or the CX register is zero. SCASB can search for a character in an array & if found, it will be replaced with the desired character. 55

STRING AND TABLE OPERATIONS 56

STRING AND TABLE OPERATIONS 57

STRING AND TABLE OPERATIONS XLAT instruction and look-up tables A table is commonly referred to as a look-up table. § To access elements of a table, 8088/86 processors provide the XLAT (translate) instruction. Assume a need for a table for the values of x 2 , where x is between 0 and 9. § First the table is generated and stored in memory: § To access the square of any number from 0 to 9, by use of XLAT, register BX must have the offset address of the look-up table, and the number whose square is sought must be in the register AL. After XLAT execution, AL will have the square of the number. 58

STRING AND TABLE OPERATIONS To get the square of 5 from the table: § After execution AL will have 25 (19 H), the square of 5. § XLAT is one instruction, equivalent to the following: 59

STRING AND TABLE OPERATIONS Code conversion using XLAT can translate the hex keys of non-ASCII keyboards to ASCII. § Assuming keys are 0–F, the following is the program to convert the hex digits of 0–F to their ASCII equivalents. 60

MEMORY AND MEMORY INTERFACING 61

OBJECTIVES Define the terms capacity, organization, and speed as used in semiconductor memories. Calculate the chip capacity and organization of semiconductor memory chips. Diagram methods of address decoding for memory chips. Diagram the memory map of the IBM PC in terms of RAM, VDR, and ROM allocation. Describe the checksum method of ensuring data integrity in ROM. Describe the parity bit method of ensuring data integrity in DRAM. Describe 16 -bit memory design and related issues. 62

SEMICONDUCTOR MEMORY FUNDAMENTALS In the design of all computers, semiconductor memories are used as primary storage for data and code. They are connected directly to the CPU and they are the memory that the CPU asks for information (code or data) Among the most widely used are RAM and ROM Memory Capacity § The number of bits that a semiconductor memory chip can store is called its chip capacity (bits or bytes) Memory Organization § Each memory chip contains 2 x locations where x is the number of address pins on the chip § Each location contains y bits, where y is the number of data pins on the chip § The entire chip will contain 2 x * y bits § Ex. Memory organization of 4 K x 4: 212 = 4096 locations, each location holding 4 bits Memory Speed (access time) 63

SEMICONDUCTOR MEMORY FUNDAMENTALS Memory capacity The number of bits a semiconductor memory chip can store is called its chip capacity. § In units of K bits (kilobits), M bits (megabits), etc. Memory capacity of a memory IC chip is always given in bits. § Memory capacity of a computer is given in bytes. 64

SEMICONDUCTOR MEMORY FUNDAMENTALS MEMORIES memory organization Memory chips are organized into a number of locations within the IC. § Each can hold 1, 4, 8, or even 16 bits. Depending on internal design. § The number of bits each location can hold is always equal to the number of data pins on the chip. § The number of locations in a memory chip depends on the number of address pins. § Always 2 x , where x is the number of address pins. 65

SEMICONDUCTOR MEMORIES Each memory IC chip contains 2 x locations, where x is the number of chip address pins. Each location contains y bits, where y is the number of data pins on the chip. § The entire chip contains 2 x x y bits, where x is the number of address pins and y the number of data pins. The 2 x x y is referred to as the organization of the memory chip, with x expressed as the number of address pins, and y the number of data pins. § 2 10 = 1024 = 1 K. (Kilo = 1000. 1 Kilobyte) Note that in common speech, 1 K is 1000, but in computer terminology it is 1024. See Table 10 -1. 66

MEMORY PIN CONNECTIONS – address inputs – data outputs or input/outputs – some type of selection input at least one control input to select a read or write operation – For ROM only read operation 67

MEMORY ADDRESS DECODING SIMPLE LOGIC GATE AS ADDRESS DECODER In connecting a memory chip to the CPU, the data bus is connected directly to the data pins of the memory. § Control signals MEMR & MEMW are connected to the OE & WR pins. 68

MEMORY ADDRESS DECODING SIMPLE LOGIC GATE AS ADDRESS DECODER On the address buses, the lower bits of the address go directly to memory chip address pins. § The upper ones activate the CS pin of the memory chip. § CS pin, with RD/WR allows data flow in/out of the chip. § No data can be written into or read from the memory chip unless CS is activated. CS input is active-low and can be activated using simple logic gates, such as NAND and inverters. § For every block of memory, we need a NAND gate. § See Figs. 10 -9 & 10 -10 on page 266. 69

MEMORY ADDRESS DECODING SIMPLE LOGIC GATE AS ADDRESS DECODER Example 10 -6 shows the address range calculation for Fig. 10 -10 on page 266. § Note the output of the NAND gate is active-low. § The CS pin is also active-low. 70

MEMORY ADDRESS DECODING SIMPLE LOGIC GATE AS ADDRESS DECODER Design a memory interface using a simple NAND gate decoder that selects a 2 KB EPROM for memory location FF 800 H–FFFFFH. Solution: Memory Map A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Address in Hex 0 0 0 FF 800 H 1 1 1 FFFFFH A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 1 1 1 1 1 71

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER In connecting a memory chip to the CPU, the data bus is connected directly to the data pins of the memory. § Control signals MEMR & MEMW are connected to the OE & WR pins. 72

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER In the absence of CPLD or FPGA as address decoders, the 74 LS 138 chip is an excellent choice. 73

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER The need for NAND and inverter gates is eliminated when using 74 SL 138. 74

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER To enable 74 SL 138: G 2 A = 0, G 2 B = 0, G 1 = 1. § G 2 A & G 2 B are grounded; G 1 = 1 selects this 74 LS 138. 75

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER A circuit that uses eight EPROMs for a 64 K 8 section of memory in an 8088 microprocessor-based system. The addresses selected in this circuit are F 0000 H–FFFFFH. 76

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER Interface 512 KB RAM to 8088 MP using 64 KB RAM using 3: 8 decoder with starting address of memory as 80000 H. Clearly mention decoder logic and memory map. Solution: Calculate number IC (Chip) required Interface 512 KB RAM using 64 KB RAM so 8 IC of size 64 KB Number of address lines required to connect each IC So for 64 KB memory IC required 16 address lines i. e. A 1 5 – A 0. Memory map to find address line to be connected to the decoder (NAND or 3: 8 decoder) and also find the start and end memory address of each IC. 77

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER 78

MEMORY ADDRESS DECODING 3 X 8 DECODER AS ADDRESS DECODER Draw the interfacing diagram 79

DATA INTEGRITY IN RAM AND ROM When storing or transferring data from one place to another, a major concern is data integrity. There are many ways to ensure data integrity depending on the type of storage. § The checksum method is used for ROM. § The parity bit method is used for DRAM. § The CRC (cyclic redundancy check) method is employed for mass storage devices such as hard disks and for Internet data transfer. 80

DATA INTEGRITY IN RAM AND ROM CHECKSUM BYTE To ensure the integrity of the contents of ROM, every PC must perform a checksum calculation. § Using a checksum byte, an extra byte tagged to the end of a series of bytes of data. To calculate the checksum byte of a series of bytes: § 1. Add the bytes together and drop the carries. § 2. The 2's complement of the total sum, the checksum byte, becomes the last byte of the stored information. § 3. Add all the bytes, including the checksum byte. § The result must be zero; If it is not zero, one or more bytes of data have been changed (corrupted). § See Examples 10 -11 and 10 -12. 81

DATA INTEGRITY IN RAM AND ROM CHECKSUM BYTE 82

DATA INTEGRITY IN RAM AND ROM CHECKSUM BYTE 83

DATA INTEGRITY IN RAM AND ROM CHECKSUM BYTE When the PC is turned on, one of the first things the BIOS does is to test the system ROM. § The code for such a test is stored in the BIOS ROM. 84

DATA INTEGRITY IN RAM AND ROM CHECKSUM BYTE Note in the code how all the bytes are added together without keeping the track of carries. § The total sum is ORed with itself to see if it is zero. § The zero flag is expected to be high on return from this subroutine; If it is not, the ROM is corrupted. 85

DATA INTEGRITY IN RAM AND ROM PARITY BIT GENERATOR/CHECKER IN THE PC Parity is used to detect two types of DRAM errors: § Hard error - some bits, or an entire row of memory cells in the memory chip get permanently stuck high or low. § Thereafter always producing 1 or 0, regardless of what is written into the cell(s). § Soft error - a single bit is changed from 1 to 0 or 0 to 1. § Due to current surge or certain particle radiation in the air. Including a parity bit to ensure RAM data integrity is the most widely used, simplest & cheapest method. § This method can only indicate if there is a difference between the data written to memory, and data read. § It cannot correct the error, as some high-performance systems. 86

DATA INTEGRITY IN RAM AND ROM 74 S 280 PARITY BIT GENERATOR AND CHECKER To understand parity bit circuitry, it is necessary to understand the 74 LS 280 parity bit generator & checker chip, which has 9 inputs & 2 outputs. 87

DATA INTEGRITY IN RAM AND ROM 74 S 280 PARITY BIT GENERATOR AND CHECKER Even or odd output is activated as in Table 10 -6. § If all 9 inputs have an even number of 1 bits, the § even output goes high, as in cases 1 and 4. § If the 9 inputs have an odd number of high bits, the § odd output goes high, as in cases 2 and 3. 88

DATA INTEGRITY IN RAM AND ROM 74 S 280 PARITY BIT GENERATOR AND CHECKER Inputs A–H are connected to the data bus, 8 bits. § The I input is used as a parity bit to check the data byte read from memory. 89

DATA INTEGRITY IN RAM AND ROM 74 S 280 PARITY BIT GENERATOR AND CHECKER When a byte is written to a memory location, the even-parity bit is generated and saved on the ninth DRAM chip as a parity bit. § With use of control signal MEMW. When a byte of data is read from the same location: § The parity bit is gated into the I input through MEMR. If there is a difference between data written & read, the Q output (PCK, parity bit check) of the 74 LS 74 is activated. § Q activates NMI, indicating a parity bit error, and will display a parity bit error message. 90

16 -BIT MEMORY INTERFACING ODD AND EVEN BANKS In a 16 -bit CPU, memory locations 00000 H–FFFFFH are designated as odd and even bytes. § To distinguish between odd & even bytes, the CPU provides a signal called BHE (bus high enable). § BHE, with A 0 is used to select odd/even bytes. 91

16 -BIT MEMORY INTERFACING ODD AND EVEN BANKS In the design of current x 86 PCs, details of CPU connection to memory and other peripherals are not visible for educational purposes. § 16 -bit bus interfacing to memory chips is a detail now buried within a current PCs chipset. Concepts from 80286 apply to any 16 -bit microprocessor. 640 KB of DRAM for 16 -bit buses. 92

16 -BIT MEMORY INTERFACING ODD AND EVEN BANKS Connection for the 16 bit data bus. § Note the use of A 0 (Even banks Selector) and BHE (Odd banks Selector) as bank selectors. Also use of the 74 LS 245 chip as a data bus buffer. 93

16 -BIT MEMORY INTERFACING ACCESSING EVEN AND ODD WORDS Intel defines 16 -bit data as a word, and the address of a word can start at an even or an odd number. § In systems with a 16 -bit data bus, accessing a word from an odd addressed location can be slower. In the instruction “MOV AX, [2000]” the address of the word being fetched into AX starts at an even address. In the case of “MOV AX, [2007]” the address starts at an odd address. 94

16 -BIT MEMORY INTERFACING ACCESSING EVEN AND ODD WORDS In the 8 -bit system, accessing a word is treated like accessing two bytes. § Regardless of whether the address is odd or even. 95

16 -BIT MEMORY INTERFACING ACCESSING EVEN AND ODD WORDS In the 16 -bit system, accessing a word with an even address takes one memory cycle. That is because one byte is carried on DO - D 7 and the other on D 8 - D 15 in the same memory cycle. However, accessing a word with an odd address requires two memory cycles. For example, see how accessing the word in the instruction "MOV AX, [F 617 H]“ as show in diagram 96

16 -BIT MEMORY INTERFACING ACCESSING EVEN AND ODD WORDS Memory Address Data Type BHE FF 616 H FF 617 H Byte Word Byte FF 616 H Word 1 0 0 0 1 A 0 Memory Cycle Data Lines Used 0 0 1 1 0 One One First Cycle Second Cycle D 7 – D 0 D 15 – D 8 D 7 – D 0 Bank Selected/E nable Even Bank Both Bank Odd Bank Even Bank 97

16 -BIT MEMORY INTERFACING ACCESSING EVEN AND ODD WORDS It is the EVEN directive and is used to locate the data/code on even address location This ensures that VALUE 1, a word-sized operand, is located in an even address location. So, an instruction such as "MOV AX, VALUE 1" § "MOV VALUE 1, CX", will take only a single memory cycle. 98

16 -BIT MEMORY INTERFACING ODD AND EVEN BANKS E. g. Interface 8 Kx 8 ROM and 4 Kx 8 RAM to 8086 microprocessor. Assume that the starting address for ROM is 40000 H and that for RAM is 44000 H. Solution: Calculate number IC (Chip) required One IC of 8 KB ROM and one IC of 4 KB RAM A 0 address line used to enable Even bank and BHE line used to enable the Odd bank Number of address lines required to connect each bank 8 KB ROM IC requires 13 address lines i. e. A 1 2 – A 0 and 4 KB RAM IC so it requires 12 address lines i. e. A 1 1 – A 0 But 8 KB ROM IC is divided into two banks each of size 4 KB so it requires 12 address lines i. e. A 1 2 – A 1 similarly 4 KB RAM IC is divided into two bank each of size 2 KB it required 11 address lines i. e. A 1 1 – A 1. Memory map to find address line to be connected to the decoder (NAND or 3: 8 decoder) and also find the start and end memory address of each IC. 99

16 -BIT MEMORY INTERFACING ODD AND EVEN BANKS 100

16 -BIT MEMORY INTERFACING ODD AND EVEN BANKS 101

16 -BIT MEMORY INTERFACING MEMORY CYCLE TIME & INSERTING WAIT STATES To access an external device such as memory or I/O, the CPU provides a fixed amount of time called a bus cycle time. § During this time, the read & write operation of memory or I/O must be completed. Bus cycle time used for accessing memory is often referred to as MC (memory cycle) time. The time from when the CPU provides addresses at its address pins, to when the data is expected at its data pins is called memory read cycle time. 102

16 -BIT MEMORY INTERFACING MEMORY CYCLE TIME & INSERTING WAIT STATES In all x 86 CPUs from the 286 to the Pentium, the memory cycle time is only 2 clocks. If memory is slow and its access time does not match MC time of the CPU, extra time can be requested from the CPU to extend the read cycle. § Called a wait state (WS). To avoid too many wait states in interfacing memory to CPU, cache memory & other high-speed DRAMs were invented. 103

16 -BIT MEMORY INTERFACING MEMORY CYCLE TIME & INSERTING WAIT STATES 104

16 -BIT MEMORY INTERFACING MEMORY CYCLE TIME & INSERTING WAIT STATES Memory access time is not the only factor in slowing down the CPU, even though it is the largest one. Delay associated with reading data stored in memory has the following two components: § 1. The time taken for address signals to go from CPU pins to memory pins, going through decoders and buffers (e. g. , 74 LS 245). This, plus the time it takes for the data to travel from memory to CPU, is referred to as a path delay. § 2. The memory access time to get the data out of the memory chip. This is the largest of the two components. The total sum of these two must equal the memory read cycle time provided by the CPU. Memory access time is the largest and takes about 80% of the read cycle time. 105

16 -BIT MEMORY INTERFACING MEMORY CYCLE TIME & INSERTING WAIT STATES 106

16 -BIT MEMORY INTERFACING BUS BANDWIDTH The main advantage of the 16 -bit data bus is a doubling of the rate of transfer of information between the CPU and the outside world. § The rate of data transfer is called bus bandwidth. The wider the data bus, the higher the bus bandwidth. Bus bandwidth is measured in MB (megabytes) per second and is calculated as follows: There are two ways to increase the bus bandwidth: § Use a wider data bus, shorten bus cycle time, or do both. While the data bus width has increased from 16 -bit in the 80286 to 64 -bit in the Pentium, the bus cycle time is reaching a maximum of 133 MHz. 107

16 -BIT MEMORY INTERFACING BUS BANDWIDTH 108

8255 I/O PROGRAMMING 109

OBJECTIVES Code Assembly language instructions to read and write data to and from I/O ports. Diagram the design of peripheral I/O using the 74 LS 373 output latch and the 74 LS 244 input buffer. Describe the I/O address map of x 86 PCs. List the differences in memory-mapped I/O versus peripheral I/O. Describe the purpose of a simple programmable peripheral interface chip. 110

8086/88 INPUT/OUTPUT INSTRUCTIONS All x 86 processors, 8088 to Pentium®, can access external devices called ports using I/O instructions. § Memory can contain both opcodes and data. § I/O ports contain data only Two instructions: “OUT” and “IN” send data from the accumulator (AL or AX) to ports or bring data from ports into the accumulator. 111

8086/88 INPUT/OUTPUT INSTRUCTIONS 8 -BIT DATA PORTS 8088 I/O operation is applicable to all x 86 CPUs. § The 8 -bit port uses the D 0–D 7 data bus for I/O devices. Register AL is used as the source/destination for IN/OUT instructions. § To input or output data from any other registers, the data must first be moved to the AL register. Instructions OUT and IN have the following formats: 112

8086/88 INPUT/OUTPUT INSTRUCTIONS 8 -BIT DATA PORTS In format (1) – § port# is the address of the port and can be from 00 to FFH, allowing up to 256 input and 256 output ports. § In this format, the 8 -bit port address is carried on address bus A 0 -A 7. § No segment register is involved in computing the address. In format (2) – § port# is the address of the port and can be from 0000 to FFFFH, allowing up to 65, 536 input and 65, 536 output ports. § In this format, the 16 - bit port address is carried on the address bus A 0 -A 15. § The use of a register as a pointer for the port address has an advantage in that the port address can be changed very easily, especially in. cases of dynamic compilations where the port address can be passed to DX. 113

8086/88 INPUT/OUTPUT INSTRUCTIONS HOW TO USE I/O INSTRUCTIONS 16 -bit peripheral devices. § Printers, hard disks, and keyboards. For an 8 -bit port, use immediate addressing: 114

8086/88 INPUT/OUTPUT INSTRUCTIONS HOW TO USE I/O INSTRUCTIONS 16 -bit port address instruction addressing mode with register DX. using register indirect § This program toggles port address 300 H continuously. § Only DX can be used for 16 -bit I/O addresses. § Use register AL for 8 -bit data. 115

8086/88 INPUT/OUTPUT INSTRUCTIONS HOW TO USE I/O INSTRUCTIONS 116

I/O ADDRESS DECODING AND DESIGN The concept of address bus decoding for I/O instructions is exactly the same as for memory. § 1. The control signals IOR and IOW are used along with the decoder. § 2. For an 8 -bit port address, A 0–A 7 is decoded. § 3. If the port address is 16 -bit (using DX), A 0–A 15 is decoded. 117

I/O ADDRESS DECODING AND DESIGN USING 74 LS 373 IN AN OUTPUT PORT DESIGN 74 LS 373 can be used as a latching system for simple I/O ports. § Pin OC must be grounded. 118

I/O ADDRESS DECODING AND DESIGN USING 74 LS 373 IN AN OUTPUT PORT DESIGN For an output latch, it is common to AND the output of the address decoder with control signal IOW. § To provide the latching action. 119

I/O ADDRESS DECODING AND DESIGN USING 74 LS 373 IN AN OUTPUT PORT DESIGN 120

I/O ADDRESS DECODING AND DESIGN IN PORT DESIGN USING 74 LS 244 Data from a data bus, must come in through a three-state buffer—referred to as tristated. § Simple input ports we use the 74 LS 244 chip. Since 1 G & 2 G each control only 4 bits of 74 LS 244, they both must be activated for 8 -bit input. 121

I/O ADDRESS DECODING AND DESIGN IN PORT DESIGN USING 74 LS 244 is widely used for buffering and providing high driving capability for unidirectional buses. 122

I/O ADDRESS DECODING AND DESIGN IN PORT DESIGN USING 74 LS 244 as an entry port to the system data bus. 123

I/O ADDRESS DECODING AND DESIGN MEMORY-MAPPED I/O Communicating with I/O devices using IN and OUT instructions is referred to as peripheral I/O. § Some designers also refer to it as isolated I/O. Some processors do not have IN & OUT instructions, but use Memory-mapped I/O. 124

I/O ADDRESS DECODING AND DESIGN MEMORY-MAPPED I/O Difference between the memory mapped I/O and I/O mapped I/O (Isolated I/O or Peripheral I/O) 125

I/O ADDRESS DECODING AND DESIGN MEMORY-MAPPED I/O Memory-Mapped I/O Isolated (Peripheral ) I/O The IN and OUT instructions transfer data between the microprocessors accumulator or memory and the I/O device. Instructions that access memory locations are used instead of IN and OUT instructions: MOV AL, [2000] will access the input port & MOV [2000], AL will access the output port. Entire 20 -bit address, A 0 -A 19, must be decoded (decoding circuitry is expensive); Hence DS must be loaded before accessing memory-mapped I/O: Only A 0 -A 15 are decoded; Hence, DS initialization is not required; decoding circuitry may be less expensive. MEMR and MEMW control signals are used. IOR and IOW control signals are used. The number of ports can be as high as 220 (1, 048, 576). Limited only to 65, 536 input and output ports Arithmetic and logic operations can be performed directly, without moving data to accumulator. Data should be moved to accumulator for any kind of operations. Uses memory address space, which could lead to memory space fragmentation. The user can expand the memory to its full size 126 without using any memory space for I/O devices.

I/O ADDRESS DECODING AND DESIGN Use a 74 ALS 138 decoder that decodes 8 -bit I/O ports F 0 H F 7 H. Port/Memory Map Table 127

I/O ADDRESS DECODING AND DESIGN Interface diagram 128

I/O ADDRESSES MAP OF X 86 PC’S Designers of the original IBM PC decided to make full use of I/O instructions. To be compatible with the x 86 IBM PC, follow the I/O map of shown in next slide. The address range 300– 31 FH is set aside for prototype cards to be plugged into the expansion slot. 129

I/O ADDRESSES MAP OF X 86 PC’S 130

I/O ADDRESSES MAP OF X 86 PC’S ABSOLUTE VS LINEAR ADDRESS DECODING In decoding addresses, either all or a selected number of them are decoded. § In absolute decoding, all address lines are decoded. § If only selected address pins are decoded, it is called linear select decoding. Linear select is cheaper, but creates aliases, the same port with multiple addresses. § If you see a large gap in the I/O address map of the x 86 PC, it is due to the address aliases of the original PC. 131

I/O ADDRESSES MAP OF X 86 PC’S PROTOTYPE ADDRESSES 300– 31 FH IN X 86 PC Prototype cards at 300 H– 31 FH can be data acquisition boards used to monitor analog signals. § Temperature, pressure, etc. , inputs use signals on the 62 -pin section of the ISA expansion slot. 132

I/O ADDRESSES MAP OF X 86 PC’S PROTOTYPE ADDRESSES 300– 31 FH IN X 86 PC Use of Simple Logic Gates as Address Decoders: The following Fig shows the circuit design for a 74 LS 373 latch connected to port address 300 H of an x 86 PC via an ISA expansion slot. 133

I/O ADDRESSES MAP OF X 86 PC’S PROTOTYPE ADDRESSES 300– 31 FH IN X 86 PC Use of 74 LS 138 as a decoder 74 LS 138 showing I/O address decoding for an input port located at address 304 H. § Each Y output controls a single I/O device. § Y 4 output, together with the signal at IOR, controls the 74 LS 244 input buffer. 134

I/O ADDRESSES MAP OF X 86 PC’S PROTOTYPE ADDRESSES 300– 31 FH IN X 86 PC Time Delay Generation Certain amount time or delay is associated with the execution of the instruction. The execution of the instruction gives a means of generation of time delay Consider the following instruction MOV CX, 100 BACK : LOOP BACK To increase the delay using one more register. Example: MOV DX, 200 AGAIN: MOV CX, 100 BACK : LOOP BACK DEC DX JNZ AGAIN 135

PROGRAMMING AND INTERFACING THE 8255 The 8255 is a widely used 40 -pin, DIP I/O chip. § It has three separately accessible programmed ports, A, B & C. § Each port can be programmed to be input or output. § Ports can also be changed dynamically. § It also called PPI (programmable peripheral interface). 136

PROGRAMMING AND INTERFACING THE 8255 Port A (PA 0 -PA 7): § This 8 -bit port A can be programmed all as input or all as output. Port B (PB 0 -PB 7): § This 8 -bit port B can be programmed all as input or all as output. Port C (PC 0 -PC 7): § This 8 -bit port C can be programmed all as input or all as output. § It can also be split into two parts; CU (upper bits PC 4 -PC 7) and CL (lower bits PC 0 -PC 3). Each can be used as input or output. § Any bit of Port C can be programmed individually. 137

PROGRAMMING AND INTERFACING THE 8255 RD and WR - active-low 8255 control signal inputs. § If the 8255 is using peripheral I/O, IOR & IOW of the system bus are connected to these two pins. § If memory-mapped I/O, MEMR & MEMW activate them. RESET - an active-high signal input into the 8255, used to clear the control register. § All ports are initialized as input ports. 138

PROGRAMMING AND INTERFACING THE 8255 A 0, A 1, and CS § CS (chip select) selects the entire chip. § Address pins A 0 and A 1 select the specific port within the 8255. § These three pins are used to access ports A, B, C, or the control register. The control register must be programmed to select the operation mode of the three ports A, B, and C. 139

PROGRAMMING AND INTERFACING THE 8255 MODE SELECTION OF THE 8255 A 8255 ports can be programmed in various modes. § § Below shows the control word format The simple I/O mode, Mode 0, is most widely used. Any of the ports A, B, CL & CU are programmable as input or output. All bits are out or all are in. No control of individual bits 140

PROGRAMMING AND INTERFACING THE 8255 MODE SELECTION OF THE 8255 A 141

PROGRAMMING AND INTERFACING THE 8255 MODE SELECTION OF THE 8255 A The 8255 shown in Figure, is configured as follows: port A as input, B as output, and all the bits of port C as output. (a) Find the port addresses assigned to A, B, C, and the control register. (b) Find the control byte (word) for this configuration. (c) Program the ports to input data from port A and send it to both ports B and C. 142

PROGRAMMING AND INTERFACING THE 8255 MODE SELECTION OF THE 8255 A 143

External Resources https: //nptel. ac. in/courses/108/105/108105102/ https: //www. youtube. com/watch? v=Pwa. CYsm 5840&list=UUAyj. Lko. QSx. THN 3 zl. Thxg 6 w&index=26 144