Microprocessorbased Systems Course 3 A simple computer structure
Microprocessor-based Systems Course 3 A (simple) computer structure 1
Instruction format Operation code - Without explicit operands Operand 1 - Address - With one operand Operand 2 - Address/Data - With 2 operands Result - Address - With 2 operands and a result 2
Addressing modes ¡ How the operand is determined l Immediate addressing – for constants ¡ l Direct addressing – for simple variables ¡ l ADD [ESI+500 h], AX Based addressing – for records ¡ l SUB EBX, [100 h] Indexed addressing – for vectors ¡ l MOV EAX, 1234 h AND EDX, [EBX+200 h] Mixed (based and indexed) – for complex data structures ¡ OR ECX, [ESI+EBX+100 h] 3
The instruction set of a simple computer 7 6 Op. code 5 0 Address field Instruc Instr. tion code Explanations JMP 01 addr PC=addr ADD 10 addr A=A+M[addr] MEM 11 addr M[addr]=A Op. code: 7 6 5 4 3 2 1 0 0 0 abc x x x 00 01 10 11 000 001. . . 111 NOP 00 000 xxx - CLA 00 001 xxx A=0 CPL 00 010 xxx A=Not A SHR 00 011 xxx A=A>>1 SHL 00 100 xxx A=A<<1 SKIPO 00 101 xxx If A 0=1 NP++ SKIPN 00 110 xxx If A 7=1 NP++ STOP 00 111 xxx Stop the clock 4
The general scheme of a simple computer Address display STOP START Clock gen. INIT Data display Sel_Op Sel_I/D Ld_IR CLK IR – instruction reg. Phase gen. OC OC/Addr 1 M Wr. M UAL 0 Decoder and comand block micocomands M U X Man/ Auto MUX Program counter Ld. PC Inc. PC A MUX Man/ Auto SHR Ld_A SHL Rst. A Front panel Addr. switches Data switches 5
Decomposition of instructions into phases INIT I 1 Sel_I/D=0 Ld_IR I 2 Inc. PC E 1 JMP Ld. PC ADD Sel_I/D=1 Sel_op=0 MEM E 1 NOP Sel_I/D=1 CLA Rst. A CPL SHR SHL SKIPO 1 Sel_op=1 Inc. PC E 2 E 2 SHR SHL A 0 0 Wr. M Ld. A 1 Inc. PC STOP A 7 0 E 2 Ld. A SKIPN E 2 STOP 6
Phase generator (PG), Instruction decoder (ID) and Command control block (CCB) RI 7 6 5 4 32 1 0 I 1 I 2 E 1 E 2 2 DEC 3 DEC 00 CLK CG Modulo 4 counter MEM JMP ADD INIT a. Phase generator DEC Stop NOP b. Instruction decoder I 1 I 2 E 1 E 2 MEM NOP ADD CCB Sel_I/D = E 1 (ADD + MEM) STOP MEM Sel_I/D E 1 microcommands a. The contro and command block b. Implementation of the Sel_I/D cmd. 7
Sequential execution of instructions (Scalar architecture) ¡ Execution phases of an instruction: Instruction fetch (IF) Instruction decode (ID) Execution (Ex) Memory operation (Mem) Write back (Wr) 1. 2. 3. 4. 5. IF ID Ex Me Wr Instr. 1 l IF ID Ex Instr. 2 Me Wr IF ID Ex Me Wr Instr. 3 CPI = 5 8
Parallel instruction execution on a pipeline architecture (assembly line) T 1 IF T 2 T 3 T 4 ID Ex Mem T 5 Wr instruction i 1 T 6 IF T 7 ID T 8 T 9 T 10 Ex Mem Wr T 8 T 9 T 10 instruction i 2 Sequential execution CPI = 5 T 1 IF i 1 i 2 i 3 T 2 ID T 3 Ex T 4 Mem T 5 Wr IF ID Ex Mem IF i 4 ID IF i 6 T 7 Wr Ex Mem ID Ex Mem Wr ID Ex Mem IF Wr Wr Parallel execution CPI=1 (ideal case) Comparison between sequential and pipeline execution 9
Example of a pipeline architecture Instr. mem. instr. addr IR Reg. block. A R B Data mem. M addr. Reg. block Di D I P C +4 IF D e c ID ex me wr wr C 1 C 2 C 3 Ex A CPU with a pipeline structure Mem Wr 10
Hazard cases in pipeline architecture ¡ Data hazard l l IF ID IF Ex Data dependency between consecutive instructions Solutions: ¡ Idle states, multiple registers, instruction reordering Mem MOV Wr ID Ex Wr IF ID Ex IF ADD Wr ID Ex Mem AX, 5 BX, AX SUB CX, 5 MOV DX, CX 11
Hazard cases in pipeline architecture ¡ Control hazard l l JE Caused by jump/branch instructions Solutions: branch prediction, memorize previous jumps et 1 ADD AX, BX SUB CX, DX IF ID IF Ex ID Wr Ex Wr . . . . et 1: MOV SI, 1234 h IF ID Ex Mem Wr 12
Hazard cases in pipeline architecture ¡ Structural hazard l l Two different phases of consecutive instructions require the same structural unit (e. g. ALU, memory, etc. ) Solutions: Idle states, instruction reordering, multiple structural units (e. g. multiple execution units, ALUs, data memory and instruction memory) IF ID IF Ex ID Mem Wr Ex Wr 13
Superscalar and superpipeline architectures T 1 T 2 T 3 T 4 T 5 T 6 instr. i IF ID Ex Mem Wr instr. i+1 IF ID Ex Mem Wr instr. i+2 IF ID Ex Mem Wr instr. i+3 IF ID Ex Mem Wr T 1 instr. i+1 instr. i+2 instr. i+3 T 2 IF T 3 ID IF T 4 Ex ID IF T 6 Mem Wr Ex ID IF T 5 a. Superscalar architecture CPI=1/2 Ex Mem Wr ID b. Superpipeline architecture CPI=1/2 Mem Wr Ex Mem Wr Comparison between superscalar and superpipeline architectures 14
Scheduling instruction execution ¡ ¡ Objective: reordering instruction execution in order to avoid hazard situations and increase performance Static scheduling: l l Reordering in the compilation phase Instructions are grouped in Very Long Instruction Words ¡ ¡ VLIW – Very Long Instruction Word Dynamic scheduling: l l Reordering during the execution of a program Techniques: data flow analysis, dependency trees, branch predictions 15
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