Microprocessor History created by Gaurav Shrivastava gaurav 9915969367ymail
Microprocessor History created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - Visit for more Learning Resources
Early microprocessors PMOS technology – slow and awkward to interface with TTL family 4 bit processor Instructions were executed in about 20 µs. Intel 4004 the first MP. 4 K nibbles address space. Intel 8008 - can manipulate a whole byte. 16 Kbytes address space 50, 000 operations/second. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
N-channel MOSFET 1970. Faster than P-MOS. Work with +ve supply; easy to interface with TTL. 1973 Intel 8080 MP. 500, 000 operations/second. 64 K bytes memory. Upward software compatible with 8008. Other brands are MC 6800, Fairchild’s F-8 etc. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Basic types of MP Two types Single component microprocessors Bit sliced microprocessors Can be cascaded to allow functioning systems with word size from 4 bits to 200 bits. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Single component M Computer Composed of A processor read only memory (for program storage) Read/Write memory (for data storage) Input/output connections for interfacing Timer as event counter Intel 8048, Motorola 6805 R 2. Oven, washing machine, dish washer etc. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Modern MP 8, 16, 32, 64 bits are available. Intel 8085, Motorola 6800 – 8 bit word 16 bit address. Intel 8088, 8086, Motorola 68000 – 16 bits word, 20 bits address. 80186 – never used. 286 – real mode and protected mode; 16 MB memory 386 – paging, 4 GB memory, 32 bits word 486 – math coprocessor, L 1 cache created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Modern MP Pentium 64 bits i/o off the chip but process 32 bits word, exception floating point processed 64 bits, cache doubled, instruction pipelining. Pentium Pro L 2 cache, Improved pipelining Pentium MMX Multi-Media extensions, 57 new inter instruc mostly used for multimedia programming Pentium II, IV Pentium pro with MMX tech, increased L 2 cache, full 64 bit operation RISC Reduced instruction set processor, uniform length instruc, faster in operation, cannot perform may different thing as CISC. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Basic MP architecture Fetch, decode, Control Bus FFFF 0 H for 8086, 8088 control Address Bus created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - Register Array 0000 H for 8085 Instruction Register ALU execute. PC increment. First instruction is a fetch Data Bus AF, BC, DE, HL, SP, PC many more
Memory Interfacing and IO decoding created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Interfacing needs bus Isolation and separation of signals from different devices connected to MP. Unidirectional Bidirectional LS 373, 244 created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Memory map Pictorial representation of the whole range of memory address space. Defines which memory system is where, their sizes etc. Address space or range. 8086 has 1 M address space in minimum mode. 8085 has 64 K address sspace. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Address Decoding Address decoder is a digital ckt that indicates that a particular area of memory is being addressed, or pointed to, by the MP. Absolute address decoding Decode an address to one single output Decode 10110 so that u can get a signal from the decoder when it receives exactly that bit pattern. Partial address decoding Some bits are used as don’t care so that decoder gives a signal for a range of consecutive bit patterns. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Absolute decoding 10 11 0 10110 abcde Active low o/p signal Can use decoder IC with gates to achieve exact decoded o/p 1 0 1 3 to 8 line dcd 0 o/p 7 Logic 1 created by : Gaurav Shrivastava gaurav 9915969367@ymail. com 8 input NAND gate implementation contact: -
Partial decoding When a range of addresses are deconded then it is called partial decoding. For example, if we need to generate a control signal for an address generated by the MP within the range FFF 0 – FFFF, then it is called partial decoding. A 15 1111 xxxx A 14 A 4 Decoder, multiplexer can be used for address decoding created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Internal architecture of 8085 ALU created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Flag register S Z AC P CY created by : Gaurav Shrivastava gaurav 9915969367@ymail. com 1. S : after the execution of an arithmetic operation, if bit 7 of the result is 1, then sign flag is set. 2. Z : bit is set if ALU operation results a zero in the Acc or registers. 3. AC: bit is set, when a carry is generated by bit 3 and passed on bit 4. 4. P: parity bit is set when the result has even number of 1 s. 5. CY = carry is set when result generates a carry. Also a borrow flag. contact: -
Accumulator Hold data for manipulation (arithmetic, logical). Whenever the operation combines two words, either arithmetically or logically, the accumulator contains one word (say A) and the other word(say B) may be contained in a register or in memory location. After the operation the result is placed in the Acc replacing the word A. Major working register. MP can directly work on Acc. Programmed data tranfer. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
General purpose registers Six registers. B, C, D, E, H and L can store 8 bit data. They can be combined to perform some 16 bit operation. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
ALU Arithmetic logic unit. Two input ports, one output port. Perform AND, OR, Ex. OR, Add, subtract, complement, Increment, Decrement, shift left, shift right. ALUs two temporary registers are connected to MPs internal bus from which it can take data from any registers. It can place data directly to data bus through its single output port. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Program counter Its job is to keep track of what instruction is being used and what the next instruction will be. For 8085 it is 16 bit long. Can get data from internal bus as well as memory location. PC automatically increments to point to the next memory during the execution of the present instruction. PC value can be changed by some instructions. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Stack pointer 16 bit register acts as memory pointer. Can save the value of the program counter for later use. points to a region of memory which is called stack. follows LIFO algorithm. After every stack operation SP points to next available location of the stack. Usually decrements. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Memory address register PC sends address to MAR points to the location of the memory where the content is to be fetched from. PC increments but MAR does not. If the content is an instruction, IR decodes it. During execution if it is required to fetch another word from memory, PC is loaded with the value PC again sends it to the MAR and fetch operation starts. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Instruction register Holds instruction the micro is currently being executed. 8 bit long. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
others Instruction decoder. Control logic. Internal data bus. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
5 V 8085 40 pin DIP. GND 40 20 SID 5 SOD 4 +5 V 3 - 5 MHz X 1 X 2 21 – 28 HIGH ORDER ADD BUS TRAP 6 RST 7. 5 7 ADD BUS DATA BUS CONTROL STATUS POWER SUPPLY AND FREQ EXTERNALLY INITIATED SIGNALS SERIAL I/O PORTS 12 – 19 MUX ADD/ DATA BUS RST 6. 5 8 RST 5. 5 9 INTR 10 30 ALE 29 S 0 READY 35 HOLD 39 33 S 1 RESET IN 36 34 IO/M’ 32 RD’ INTA 11 HLDA 38 created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - 3 RESET OUT 37 31 WR’ CLK OUT
ADD/DATA bus Address bus 16 bits A A 8 to A 15 unidirectional. Higher 8 bit 15 Addresspins bus. are AD 0 to AD 7 multiplexed with data. This bidirectional when used as data bus. higher 8 bit Data bus 8 bit long: AD 0 to AD 7 A 8 ALE AD 7 AD 6 AD 5 AD 0 G D Q’ Address bus. Lower 8 bit OC GND Data bus created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Control signals ALE – active high output used to latch the lower 8 address bits. RD, WR - active low output signals. IO/M – output signal to differentiate memory and IO operation. S 1 and S 0 – status output signal. Identify various operations. Machine cycle IO/M’ S 1 S 0 Control signals Opcode fetch 0 1 1 RD=0 Memory read 0 1 0 RD=0 Memory write 0 0 1 WR=0 I/O read 1 1 0 RD=0 I/O write 1 0 1 WR=0 Interrupt Ackn 1 1 1 INTA=0 Halt Z 0 0 Hold Z X X Reset Z X X RD, WR =Z and INTA=1 created by : Gaurav Shrivastava contact: -gaurav 9915969367@ymail. com
External control signals INTR – interrupt request. Input signal INTA – interrupt acknowledge. o/p signal. RST 7. 5, RST 6. 5, RST 5. 5 – restart interrupts. Vectored interrupts. Higher priority. TRAP - Nonmaskable interrupt. Highest priority. Hold – request for the control of buses. O/P signal HLDA – Hold Acknowledge. I/P signal READY – I/P signal. When low Mp waits for integral number of clock cycles until it goes high. created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
Bus control signals MEMR IO/M IOWR RD 8085 MEMWR WR IOWR created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
8080 functional block diagram Serial I/O control Interrupt control Accumu MUX Temp Reg Instru Register (8) Instru Decoder Reg Select Flags W Z Temp Reg (8) B C (8) D E (8) H L (8) Stack pointer (16) Program counter (16) Incrementer/decrementer Latch (16) Address buffer (8) Timing & control created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - Data/Add buffer (8)
Timing diaga. of Memory cycle T 1 T 2 T 3 CLK A 15 -A 8 A 7 -A 0 Data from memory AD 7 -AD 0 A 7 -A 0 Data from MPU ALE IO/M RD MEMRD WR MEMWR READ Cyclecreated by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - WRITE Cycle
Interfacing A Memory Chip • 2 K Byte memory • Memory address space of the chip: 8800 H to 8 FFFH A 14 A 15 IO/M A 13 A 12 A 11 E 2 E 3 3 to 8 decoder Q 1 A 10 A 9 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1 0 8 0 0 1 X X X 8 -F 0 -F A 0 RD WR 0 -F created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - MEMSEL CE Memory Chip D 7 D 6 D 0
MVI A, 32 H Instruction 2000 H 2001 H 3 EH ; MVI A, 32 H M 1 (Opcode-fetch) T 1 A 15 -A 8 AD 7 -AD 0 T 2 T 3 20 H; high-order address 00 H; loworder Add M 2 (Memory Read) T 4 T 1 Unspecified 3 E; opcode T 3 T 2 20 H; High-order address 01 H; loworder Add 32 H; Data ALE Status IO/M=0, S 1=1, S 0=1; opcode fetch Status IO/M=0, S 1=1, S 0=0; data read RD created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
OUT/IN instruction port address: 50 H 2050 D 3 OUT 50 H sends acc content to I/O address 50 H 2051 50 Let input port address is 30 H 2150 DB IN 30 H reads content from I/O address 30 H and 2151 30 stores the value in accum created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
IN 30 H instruction M 1 T 2 M 2 T 3 T 4 T 1 T 2 M 3 T 1 T 2 T 3 CLK A 15 -A 8 AD 7 -AD 0 unspec ified 21 H 50 H DB from memory 21 H 51 H Port add 30 H Port addre 30 H ALE IO/M RD MEMRD IORD created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - Port add 30 H Data from Accumula
OUT 50 H instruction M 1 T 2 M 2 T 3 T 4 T 1 T 2 M 3 T 1 T 2 T 3 CLK A 15 -A 8 AD 7 -AD 0 unspec ified 20 H 50 H Opcode D 3 20 H 51 H Port add, 50 H Port addre 50 H ALE IO/M RD MEMRD IOWR created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: - Port add 50 H Data from Accumula
created by : Gaurav Shrivastava gaurav 9915969367@ymail. com IOR or IOW Decoder Enable contact: - Latch Or Tri-state Buffer To Peripherals NOR Data bus Decode the IO address. Combine it with control the signal to generate a unique IO select pulse that is generated only when both signals are asserted. Use it to activate the IO port Address decoding can be absolute or partial Address lines Device selection & Data Transfer
Interfacing LED for display Given port add: FFH Use octal latch as o/p port. Steps for IO select pulse: Decode FF Use IO/M to make the port output only Use WR signal to write data to the port created by : Gaurav Shrivastava gaurav 9915969367@ymail. com contact: -
MVI A, data OUT FFH HLT A 7 A 1 A 0 * To interface a 7 -segment display you need to decide about the type of 7 -segment: common anode or common cathode * Power supply connection to the LED segments will be opposite. * For common cathode a 0 is sent to the respective pin to lit it up. Q 7 IOSEL IO/M G A 10 A 9 D FF A 0 OE created by : Gaurav Shrivastava gaurav 9915969367@ymail. com WR contact: - +5 V
Interfacing DIP switches Let port address: 07 H – 00 H Partial decoding Must use pull-up resistors. IN 07 H instruction reads a byte into accumulator from port 07 H A 4 A 7 A 6 A 5 A 3 IO/M E 1 E 2 E 3 3 to 8 decoder Q 0 RD IOSEL OE D 7 D 1 D 0 +5 V created by : Gaurav Shrivastava contact: -gaurav 9915969367@ymail. com For more detail contact us
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