MICROCONTROLLER INSTRUCTION SET l Subject MICROCONTROLLER AND EMBEDED

MICROCONTROLLER INSTRUCTION SET l Subject: MICROCONTROLLER AND EMBEDED SYSTEM Class: 5 th, ECE

Introduction l An instruction is an order or command given to a processor by a computer program. All commands are known as instruction set and set of instructions is known as program. l 8051 have in total 111 instructions, i. e. 111 different words available for program writing.

Instruction Format l Where first part describes WHAT should be done, while other explains HOW to do it. l The latter part can be a data (binary number) or the address at which the data is stored. l Depending upon the number of bytes required to represent 1 instruction completely.

Types Of Instructions l Instructions are divided into 3 types; 1. One/single byte instruction. 2. Two/double byte instruction. 3. Three/triple byte instruction.

Types Of Instructions 1. One/single byte instructions : l If operand is not given in the instruction or there is no digits present with instruction, the instructions can be completely represented in one byte opcode. l OPCODE 8 bit

Types Of Instructions 2. Two/double byte instruction: l If 8 bit number is given as operand in the instruction, the such instructions can be completed represented in two bytes. l First byte Second byte l OPCODE 8 bit data or I/O port

Types Of Instructions 3. Three/triple byte instruction: l If 16 bit number is given as operand in the instructions than such instructions can be completely represented in three bytes 16 bit number specified may be data or address.

Types Of Instructions 1. First byte will be instruction code. 2. Second byte will be 8 LSB’s of 16 bit number. 3. Third byte will be 8 MSB’s of 16 bit number. l l l First byte Second byte Third byte OPCODE. 8 LSB’s of data/address. 8 MSB’S of data/address.

Addressing Modes l Addressing modes specifies where the data (operand) is. They specify the source or destination of data (operand) in several different ways, depending upon the situation. l Addressing modes are used to know where the operand located is.

Addressing Modes l There are 5 types of addressing modes: 1. Register addressing. Direct addressing. Register indirect addressing. Immediate addressing. Index addressing. 2. 3. 4. 5.

Register Addressing Mode l In register addressing mode; the source and/or destination is a register. l In this case; data is placed in any of the 8 registers(R 0 -R 7); in instructions it is specified with letter Rn (where N indicates 0 to 7).

Register Addressing Mode l For example; 1. ADD A, Rn (This is general instruction). 2. ADD A, R 5 (This instruction will add the contents of register R 5 with the accumulator contents).

Direct Addressing Mode l In direct addressing mode; the address of memory location containing data to be read is specified in instruction. l In this case; address of the data is given with the instruction itself.

Direct Addressing Mode l For example; 1. MOV A, 25 H (This instruction will read/move the data from internal RAM address 25 H and store it in the accumulator.

Register Indirect Addressing Mode l In register indirect addressing mode; the contents of the designated register are used as a pointer to memory. l In this case; data is placed in memory, but address of memory location is not given directly with instruction.

Register Indirect Addressing Mode l For example; 1. MOV A, @R 0 This instruction moves the data from the register whose address is in the R 0 register into the accumulator.

Immediate Addressing Mode l In immediate addressing mode, the data is given with the instruction itself. l In this case; the data to be stored in memory immediately follows the opcode.

Immediate Addressing Mode l For example; 1. MOV A, #25 H (This instruction will move the data 25 H to accumulator.

Index Addressing Mode l Offset (from accumulator) is added to the base index register( DPTR OR Program Counter) to form the effective address of the memory location. l In this case; this mode is made for reading tables in the program memory.

Index Addressing Mode l For example; 1. MOVC A, @ A + DPTR ( This instruction moves the data from the memory to accumulator; whose address is computed by adding the contents of accumulator and DPTR)

Types Of Instructions 1. 2. 3. 4. 5. Data transfer instructions. Arithmetic instructions. Logical instructions with bits. Branch instructions.

Data Transfer Instructions l These instructions move the content of one register to another one. l Data can be transferred to stack with the help of PUSH and POP instructions.

Data Transfer Instructions l MNEMONIC DESCRIPTION BYTES l MOV A, Rn (A) (Rn) 1 l MOV A, Rx (A) (Rx) 2 l MOV A, @Ri (A) (Ri) 1

Data Transfer Instructions l MOV A, #X (A) Data 2 l MOV Rn, A (Rn) (A) 1 l MOV Rn, Rx (Rn) (Rx) 2

Data Transfer Instructions l MOV Rn, #X (Rn) Data 2 l MOV Rx, A (Rx) (A) 2 l MOV Rx, Rn (Rx) (Rn) 2

Data Transfer Instructions l MOV Rx, Ry (RX) (Ry) 3 l MOV Rx, @ Ri (Rx) (Ri) 2 l MOV Rx, # X (Rx) Data 3

Data Transfer Instructions l MOV @ Ri, A (Ri) (A) 1 l MOV @ Ri, Rx (Ri) (Rx) 2 l MOV @ Ri, #X (Ri) Data 2

Data Transfer Instructions l MOV DPTR, #X (DPTR) Data 3 l MOVC A @ A+DPTR (A) (A+DPTR) 1 l MOVC A@ A+PC (A) (A+PC) 1

Data Transfer Instructions l MOVX A, @ Ri A (Ri) 1 l MOVX A, @ (A) (DPTR) 1 DPTR l MOVX @Ri, A (Ri) (A) 1

Data Transfer Instructions l MOVX @ DPTR, A (DPTR) (A) 1 l PUSH Rx Push directly addressed Rx register on stack 2 l POP Rx 2 (A) (Rx)

Data Transfer Instructions l XCH A, Rn (A) (Rn) 1 l XCH A, Rx (A) (Rx) 2 l XCH A, @Ri (A) (Ri) 1

Data Transfer Instructions l XCHD Exchange 4 lower bits in accumulator with indirectly addressed register 1

Arithmetic Instructions l These instructions perform several basic operations. After execution, the result is stored in the first operand. l 8 bit addition, subtraction, multiplication, increment-decrement instructions can be performed.

Arithmetic Instructions MNEMONICS DESCRIPTION l ADD A, Rn A = A + Rn 1 l ADD A, Rx A = A + Rx 2 l AAD A, @ Ri A = A+ Ri 1 l BYTE

Arithmetic Instructions l ADD A, # X A = A + Byte 2 l ADDC A, Rn A = A + Rn + C 1 l ADDC A , Rx A = A + Rx + C 2

Arithmetic Instructions l ADDC A, @ Ri A = A + Ri + C 1 l ADDC A, # X A = A + Byte + C 2 l SUBB A, Rn A = A – Rn – 1 1

Arithmetic Instructions l SUBB A, Rx A = A – Rx – 1 2 l SUBB A, @ Ri A = A – Ri – 1 1 l SUBB A, # X A = A – Byte – 1 2

Arithmetic Instructions l INC A A=A+1 1 l INC Rn Rn = Rn + 1 1 l INC Rx Rx = Rx + 1 2

Arithmetic Instructions l INC @ Ri Ri = Ri + 1 1 l DEC A A=A– 1 1 l DEC Rn Rn = Rn – 1 1

Arithmetic Instructions l DEC Rx Rx = Rx – 1 2 l DEC @ Ri Ri = Ri – 1 1 l INC DPTR = DPTR + 1 1

Arithmetic Instructions l MUL AB B: A = A * B 1 l DIV AB A = [A/B] 1 l DA A Decimal adjustment of accumulator according to BCD code 1

Logical Instructions l These instructions perform logical operations between two register contents on bit by bit basis. l After execution, the result is stored in the first operand.

Logical Instructions l MNEMONIC DESCRIPTION BYTE l ANL A, Rn (A) ^ (Rn) 1 l ANL A, Rx (A) ^ (Rx) 2 l ANL A, @ Ri (A) ^ (Ri) 1

Logical Instructions l ANL A, # X (A) (8 bit data) ^ (A) l ANL Rx, A (Rx) l ANL Rx, # X (Rx) (8 bit data) ^ (Rx) (A) ^ (Rx) 2 2 3

Logical Instructions l ORL A, Rn (A) + (Rn) 1 l ORL A, Rx (A) + (Rx) 2 l ORL A, @ Ri (A) + (Ri) 2

Logical Instructions l ORL Rx, A (Rx) (A) + (Rx) 2 l ORL Rx, # X (Rx) (8 bit data) + (Rx) 2 l XORL A, Rn Logical exclusive OR operation between the contents of accumulator and R register. 1

Logical Instructions XORL A, Rx Logical exclusive OR 2 operation between the contents of the accumulator and directly addressed register Rx. l XORL A, @ Ri Logical exclusive OR 1 operation between the contents of the accumulator and directly addressed register. l

Logical Instructions l l XORL A, # X Logical exclusive OR 2 operation between the contents of accumulator and the given 8 bit data. XORL Rx, A Logical exclusive OR 2 operation between the contents of the accumulator and directly addressed register Rx.

Logical Instructions l XORL Rx, # X Logical exclusive OR 3 operation between the contents of the directly addressed register Rx and the given 8 bit data. CLR A (A) 0 1 l CPL A l (A) (/A) 1

Logical Instructions l SWAP A l RLC (A 3 -0) (An + 1) (A 0) (C) (A 7 -4) 1 (An) (A 7) (An) (C) (A 7) 1 1

Logical Instructions l RR A (An) (A 7) (An + 1) (A 0) 1 l RRC A (An) (A 7) (C) (An + 1) (C) (A 0) 1

Logical Instructions On Bits l Similar to logical instructions, these instructions also perform logical operations. l The difference is that these operations are performed on single bits.

Logical Instructions On Bits l MNEMONIC l CLR bit l SETB C DESCRIPTION (C=0) BYTE 1 clear directly addressed bit 2 (C=1) 1

Logical Instructions On Bits l SETB bit addressed bit Set directly 2 l CPL C (1 = 0, 0 = 1) 1 l CPL bit addressed bit Complement directly 2

Logical Instructions On Bits l ANL C, bit Logical AND operation between Carry bit and directly addressed bit. 2 l ANL C, /bit Logical AND operation between Carry bit and inverted directly addressed bit. 2

Logical Instructions On Bits l ORL C, bit Logical OR operation between Carry bit and directly addressed bit. 2 l ORL C, /bit Logical OR operation between Carry bit and inverted directly addressed bit. 2

Logical Instructions On Bits l MOV C, bit to carry bit. Move directly addressed 2 l MOV bit, C addressed bit. Move Carry bit to directly 2

Program Flow Control Instructions l In this group, instructions are related to the flow of the program, these are used to control the operation like, JUMP and CALL instructions. l Some instructions are used to introduce delay in the program, to the halt program.

Program Flow Control Instructions l MNEMONIC l ACALL adr 11 DESCRIPTION (PC) (SP) ((SP)) (PC) + 2 (SP) + 1 (PC 7 – 0) (SP) + 1 (PC 15 -8) BYTE 2

Program Flow Control Instructions l LCALL adr 16 (PC) (SP) ((SP)) (PC) + 3 (SP) + 1 (PC 7 -0) (SP) + 1 (PC 15 -8) addr 15 -0 3

Program Flow Control Instructions l RET (PC 15 -8) (SP) (PC 7 -0) (SP) ((SP)) (SP) – 1 ((SP)) (SP) - 1 1

Program Flow Control Instructions l RET 1 (PC 15 -8) (SP) (PC 7 -0) (SP) l AJMP addr 11 (PC) (PC 10 -0) ((SP)) (SP) – 1 1 (PC) + 2 1 page address

Program Flow Control Instructions l LJMP addr 16 l SJMP rel (PC) addr 15 -0 3 short jump from 2 (from -128 to +127 locations in relation to first next instruction)

Program Flow Control Instructions l JC rel (PC) + 2 IF ( C ) = 1 THEN (PC) + rel 2 l JNC rel (PC) + 2 IF ( C) = 0 THEN (PC) + rel 2

Program Flow Control Instructions l JB bit, rel Jump if addressed bit is set. Short jump. 3 l JBC bit, rel Jump if addressed bit is set and clear it. Short jump. 3

Program Flow Control Instructions l JMP @A + DPTR (PC) l JZ rel (A) + (DPTR) (PC) + 2 IF (A) = 0 THEN (PC) + rel 1 2

Program Flow Control Instructions l JNZ rel (PC) + 2 IF (A) = 0 THEN (PC) + rel 2 l CJNE A, Rx, rel Compare the contents 3 of acc. And directly addressed register Rx. Jump if they are different. Short jump.

Program Flow Control Instructions l CJNE A, #X, rel (PC) + 3 3 IF ( A) < > data THEN (PC) + relative offset IF (A) < data THEN ( C ) 1 ELSE ( C ) 0

Program Flow Control Instructions l CJNE @ RI, # x, rel (PC) + 3 3 IF (Rn) <> data THEN (PC) + relative offset IF (Rn) < data THEN ( C ) 1 ELSE ( C ) 0

Program Flow Control Instructions l CJNE @ Ri, # X, rel (PC) + 3 3 IF ((Ri)) <> data THEN (PC) + relative offset IF ((Ri)) < data THEN ( C ) 1 ELSE ( C ) 0