Microcontroller Basics A microcontroller is a small lowcost

Microcontroller Basics • A microcontroller is a small, low-cost computer-on-a-chip which usually includes: – An 8 or 16 bit microprocessor (CPU). – A small amount of RAM. – Programmable ROM and/or flash memory. – Parallel and/or serial I/O. – Timers and signal generators. – Analog to Digital (A/D) and/or Digital to Analog (D/A) conversion. • Often used to run dedicated code that controls one or more tasks in the operation of a device or a system. • Also called embedded controllers, because the microcontroller and support circuits are often built into, or embedded in, the devices they control. • Devices that utilize microcontrollers include car engines, consumer electronics (VCRs, microwaves, cameras, pagers, cell phones. . ), computer peripherals (keyboards, printers, modems. . ), test/measurement equipment (signal generators, multimeters, oscilloscopes …). • Microcontrollers usually must have low-power requirements (~. 05 - 1 W as opposed to ~10 - 50 W for general purpose desktop CPUs) since many devices they control are battery-operated. EECC 250 - Shaaban #1 Lec # 20 Winter 99 2 -9 -2000

Microcontroller Components From sensors To actuators Displays, keyboard etc. Single Chip RAM, EPROM, EEPROM, flash Examples: Motorola’s 68 HC 11, 68 HC 12, AMD 29 K, Zilog’s Z 8, Z 80, Intel’s 8052, Microchip’s PIC Low-power, embedded versions of desktop CPUs: e. g Intel’s 80486 EECC 250 - Shaaban #2 Lec # 20 Winter 99 2 -9 -2000

A Typical Microcontroller Application: Car Cruise Control Speed Measurement EECC 250 - Shaaban #3 Lec # 20 Winter 99 2 -9 -2000

The Motorola 68 HC 12 Microcontroller A Typical 68 HC 12 has the following components on the chip: – A 16 -bit central processing unit (CPU 12): • 20 -Bit ALU. Instruction Queue. • Enhanced Indexed Addressing. Fuzzy Logic Instructions. – 32 -Kbyte Flash EEPROM with 2 -Kbyte Erase-Protected Boot Block. – 768 -Byte EEPROM. – 1 -Kbyte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write. – 8 -Channel, 8 -Bit Analog-to-Digital (A/D) Converter. – 8 -Channel Timer. – 16 -Bit Pulse Accumulator: • External Event Counting, Gated Time Accumulation. – Pulse-Width Modulator: • 8 -Bit, 4 -Channel or 16 -Bit, 2 -Channel • Separate Control for Each Pulse Width and Duty Cycle EECC 250 - Shaaban #4 Lec # 20 Winter 99 2 -9 -2000

A Typical 68 HC 12 Chip Pin-Out MC 68 HC 912 B 32 EECC 250 - Shaaban #5 Lec # 20 Winter 99 2 -9 -2000

M 68 EVB 912 B 32 Evaluation Board Layout EECC 250 - Shaaban #6 Lec # 20 Winter 99 2 -9 -2000

Motorola 68 HC 12 16 -bit Memory Address Space 0 x 0800 0 x 08 FF 0 x 0900 User Program Memory: 256 bytes User Data Memory: 256 bytes 0 x 09 FF EECC 250 - Shaaban #7 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Programming Model: Registers EECC 250 - Shaaban #8 Lec # 20 Winter 99 2 -9 -2000

A B D X Y SP PC CCR 68 HC 12 Registers 8 -bit Accumulator A 8 -bit Accumulator B 16 -bit Double accumulator D (A : B) 16 -bit Index register X 16 -bit Index register Y 16 -bit Stack pointer 16 -bit Program Counter Condition code register: S X H I N Z V C STOP instruction control bit Non-maskable interrupt control bit Half-carry status bit Maskable interrupt control bit Negative status bit Zero status bit Two’s complement overflow status bit Carry/Borrow status bit EECC 250 - Shaaban #9 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Data Types The HC 12 uses the following types of data: – – – – Bits. 5 -bit signed integers. 8 -bit signed and unsigned integers. 8 -bit, 2 -digit binary coded decimal (BCD) numbers. 9 -bit signed integers. 16 -bit signed and unsigned integers. 16 -bit effective addresses. 32 -bit signed and unsigned integers. • 5 -bit and 9 -bit signed integers are used only as offsets for indexed addressing modes. • 16 -bit effective addresses are formed during addressing mode computations. • 32 -bit integer dividends are used by extended division instructions. • Extended multiply and extended multiply-and-accumulate instructions produce 32 -bit products. EECC 250 - Shaaban #10 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Addressing Modes • • • Inherent Addressing Mode (INH). Immediate Addressing Mode (IMM). Direct Addressing Mode (DIR). Extended Addressing Mode (EXT). Indexed Addressing Modes: • • • 5 -Bit Constant Offset Indexed Addressing (IDX). Auto Pre/Post Decrement/Increment Indexed Addressing (IDX) Accumulator Offset Indexed Addressing (IDX). 9 -Bit Constant Offset Indexed Addressing (IDX 1). 16 -Bit Constant Offset Indexed Addressing (IDX 2). • Indirect Indexed Addressing: • 16 -Bit Constant Offset Indexed Addressing [IDX 2]. • Accumulator D Indirect Indexed Addressing [D, IDX]. EECC 250 - Shaaban #11 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Addressing Modes • Inherent Addressing Mode (INH): – Instructions that use this addressing mode either have no operands or all operands are in internal CPU registers. – Examples: NOP CLRA ABA ASRA ; this instruction has no operands ; clear A ; add A to B result in A ; arithmetic shift right A • Immediate Addressing Mode (IMM): – Examples: LDAA #$55 LDX #$1234 LDY #$67 ADDA #$17 ; load A with the 8 -bit value $55 ; load index register X with 16 -bit address $1234 ; load index register Y with 16 -bit address $0067 ; add the value $17 to register A, result in A EECC 250 - Shaaban #12 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Addressing Modes • Direct Addressing Mode (DIR): – Used to access operands in the memory address range $0000 through $00 FF – Examples: LDAA $55 LDX $20 STY $50 ; load register A with 8 -bit value in memory address $0055 ; load index register X with 16 -bit value in $0020, $0021 ; store value of Y to memory addresses $0050, $0051 • Extended Addressing Mode (EXT): – Used to access operands in the full 16 -bit address of the memory. – Examples: LDAA $F 03 B ; load register A with 8 -bit value from address $F 03 B LDX $0900 ; load index register X with 16 -bit value in $0900, $0901 EECC 250 - Shaaban #13 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Indexed Addressing Modes • 5 -Bit Constant Offset Indexed Addressing (IDX): – Uses an 5 -bit signed offset (range -16 to 15) which is added to the base index register (X, Y, SP, or PC) to form the effective address: – Examples: LDAA 12, X STAB – 8, Y ADDA 5, X ; load A with the byte at memory address (X) + 12 ; store the byte in B at address (Y) - 8 ; add A to the byte at (X) + 5, result in A • 9 -Bit Constant Offset Indexed Addressing (IDX 1): – Uses an 9 -bit signed offset (range -256 to 255) which is added to the base index register (X, Y, SP, or PC) to form the effective address: – Examples: LDAA $FF, X STAB – 20, Y ; load A with the byte at memory address (X) + $FF ; store the byte in B at address (Y) - 20 • 16 -Bit Constant Offset Indexed Addressing (IDX 2): – Uses an 16 -bit offset which is added to the base index register (X, Y, SP, or PC) to form the effective address. – This allows access to any address in the 64 -Kbyte address space. EECC 250 - Shaaban #14 Lec # 20 Winter 99 2 -9 -2000

Auto Pre/Post Decrement/Increment Indexed Addressing (IDX) • Predecrement and preincrement versions of the addressing mode adjust the value of the index register before accessing the memory location affected by the instruction: STAA 1, –SP STX 2, –SP ; equivalent to PSHA ; equivalent to PSHX • Post-decrement and postincrement versions of the addressing mode use the initial value in the index register to access the memory location affected by the instruction, then change the value of the index register. LDX 2, SP+ LDAA 1, SP+ ; equivalent to PULX ; equivalent to PULA EECC 250 - Shaaban #15 Lec # 20 Winter 99 2 -9 -2000

Indexed Addressing Modes Accumulator Offset Indexed Addressing (IDX): – In this indexed addressing mode, the effective address is the sum of the values in the base index register (X, Y, SP, or PC) and an unsigned offset in one of the accumulators (8 bit A, B or 16 -bit D). – Example: LDAA B, X • This instruction internally adds B to X to form the address from which A will be loaded. EECC 250 - Shaaban #16 Lec # 20 Winter 99 2 -9 -2000

Indirect Indexed Addressing • 16 -Bit Constant Offset Indexed Addressing [IDX] : – Adds a 16 -bit instruction-supplied offset to the base index register to form the address of a memory location that contains a pointer to the memory location affected by the instruction. – Example: LDAA [10, X] • In this example, X holds the base address of a table of pointers. • Assume that X has an initial value of $1000, and that the value $2000 is stored at addresses $100 A and $100 B. • The instruction first adds the value 10 to the value in X to form the address $100 A. • Next, an address pointer ($2000) is fetched from memory at $100 A. • Then, the byte value stored in location $2000 is read and loaded into the A accumulator. EECC 250 - Shaaban #17 Lec # 20 Winter 99 2 -9 -2000

Indirect Indexed Addressing • Accumulator D Indirect Indexed Addressing [D, IDX]: – Adds the value in the D accumulator to the value in the base index register to form the address of a memory location that contains a pointer to the memory location affected by the instruction. – The square brackets distinguish this addressing mode from D accumulator offset indexing. – Example: JMP [D, PC] GO 1 DC. W PLACE 1 GO 2 DC. W PLACE 2 GO 3 DC. W PLACE 3 • Assume that the value in D is $0002. • The JMP instruction adds the values in D and PC to form the address of GO 2. • Next the CPU reads the address PLACE 2 from memory at GO 2 and jumps to PLACE 2. EECC 250 - Shaaban #18 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Load & Store Instructions EECC 250 - Shaaban #19 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Transfer & Exchange Instructions EECC 250 - Shaaban #20 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Move Instructions EECC 250 - Shaaban #21 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 Addition & Subtraction Instructions EECC 250 - Shaaban #22 Lec # 20 Winter 99 2 -9 -2000

68 HC 12 BCD Instructions EECC 250 - Shaaban #23 Lec # 20 Winter 99 2 -9 -2000

HC 12 Increment & Decrement Instructions EECC 250 - Shaaban #24 Lec # 20 Winter 99 2 -9 -2000

HC 12 Compare & Test Instructions EECC 250 - Shaaban #25 Lec # 20 Winter 99 2 -9 -2000

HC 12 Logic Instructions EECC 250 - Shaaban #26 Lec # 20 Winter 99 2 -9 -2000

HC 12 Clear, Complement & Negate Instructions EECC 250 - Shaaban #27 Lec # 20 Winter 99 2 -9 -2000

HC 12 Multiplication & Division Instructions EECC 250 - Shaaban #28 Lec # 20 Winter 99 2 -9 -2000

Multiply and Accumulate Instruction EMACS • The EMACS instruction multiplies two 16 -bit operands stored in memory and accumulates the 32 -bit result in a third memory location. • Often used to implement simple digital filters. EECC 250 - Shaaban #29 Lec # 20 Winter 99 2 -9 -2000

HC 12 Bit Test & Manipulation Instructions EECC 250 - Shaaban #30 Lec # 20 Winter 99 2 -9 -2000

HC 12 Logical Shifts Instructions EECC 250 - Shaaban #31 Lec # 20 Winter 99 2 -9 -2000

HC 12 Arithmetic Shifts Instructions EECC 250 - Shaaban #32 Lec # 20 Winter 99 2 -9 -2000

HC 12 Rotate Instructions EECC 250 - Shaaban #33 Lec # 20 Winter 99 2 -9 -2000

HC 12 Short Branch Instructions The numeric range of short branch offset values is $80 (– 128) to $7 F (127) EECC 250 - Shaaban #34 Lec # 20 Winter 99 2 -9 -2000

HC 12 Short Branch Instructions The numeric range of short branch offset values is $80 (– 128) to $7 F (127) EECC 250 - Shaaban #35 Lec # 20 Winter 99 2 -9 -2000

HC 12 Long Branch Instructions The numeric range of long branch offset values is $8000 (– 32, 768) to $7 FFF (32, 767) EECC 250 - Shaaban #36 Lec # 20 Winter 99 2 -9 -2000

HC 12 Long Branch Instructions The numeric range of long branch offset values is $8000 (– 32, 768) to $7 FFF (32, 767) EECC 250 - Shaaban #37 Lec # 20 Winter 99 2 -9 -2000

HC 12 Decrement/Branch Instructions EECC 250 - Shaaban #38 Lec # 20 Winter 99 2 -9 -2000

HC 12 Jump & Subroutine Instructions EECC 250 - Shaaban #39 Lec # 20 Winter 99 2 -9 -2000

HC 12 Interrupt Instructions EECC 250 - Shaaban #40 Lec # 20 Winter 99 2 -9 -2000

HC 12 Stack Related Instructions EECC 250 - Shaaban #41 Lec # 20 Winter 99 2 -9 -2000

HC 12 Stack Related Instructions EECC 250 - Shaaban #42 Lec # 20 Winter 99 2 -9 -2000

HC 12 Condition Codes Instructions EECC 250 - Shaaban #43 Lec # 20 Winter 99 2 -9 -2000

HC 12 Example: Addition of Two Values USER_STACKTOP equ $0 a 00 org lds $0800 #USER_STACKTOP ; load stacktop ldaa adda #FIRST #SECOND ; load first byte in A ; add second value to A result in A staa ANSWER ; store result in answer End bra End ; done with program FIRST SECOND ANSWER org dc. b $0900 #$01 #$02 #$00 ; first value to add ; second value to add ; addition result Main EECC 250 - Shaaban #44 Lec # 20 Winter 99 2 -9 -2000

HC 12 Loop Example USER_STACKTOP org equ $0800 Main: lds #USER_STACKTOP ; load stacktop ldaa ldab deca incb cmpa bne #ITER #COUNT #$00 loop ; load number of iterations to perform ; load number of iterations performed already ; decrement Acc A ; increment Acc B ; Is Acc A = 0? ; No, continue with loop stab COUNT End: bra End ; done with program ITER COUNT org dc. b $0900 #$08 #$00 ; Number of loop iterations to perform ; Number of loop iterations performed loop: $0 a 00 ; Otherwise, save the count EECC 250 - Shaaban #45 Lec # 20 Winter 99 2 -9 -2000

HC 12 Data Table Example ; This program takes a table of data, and creates a new table ; which is the original table divided by 2 prog: data: count: org equ equ prog ldx ldy ldab repeat: ldaa asra staa dbne swi org table 1: table 2: $0800 $0900 10 #table 1 #table 2 #count 1, x+ 1, y+ b, repeat ; put program at address 0 x 0800 ; put data at address 0 x 0900 ; number of entries in table ; set program counter to 0 x 0800 ; Reg X points to entry to process in table 1 ; Reg Y points to entry to write to table 2 ; ACC B holds number of entries left to process ; Get table 1 entry into ACC A; inc X to next entry ; Divide by 2 ; Save in table 2; inc Y to next entry in table 2 ; Decrement number left to process; ; If not done, process next table 1 entry ; Done -- Exit data dc. b ds. b ; initialize table 1 (COUNT bytes long) $07, $ae, $4 a, $f 3, $6 c, $30, $7 f, $12, $67, $cf count ; reserve count bytes for table 2. EECC 250 - Shaaban #46 Lec # 20 Winter 99 2 -9 -2000