Merger Development Shohei Nishida KEK Private Discussion Jul

Merger Development Shohei Nishida KEK Private Discussion Jul. 26, 2013 S. Nishida (KEK) Jul. 26, 2013 Merger Development Private Discussion 1

Development • Basic board test (including Rocket I/O test) ü Leave everything to Shoji-san • Data Flow ü (need discussion) • Slow Control ü (need discussion) • Trigger, clock ü Test will be done with 64 MHz internal clock at the beginning. ü At some point, switch to FTSW. • Belle 2 Link ü After the tests above finished. ü Need to collect information. ü DAQ people can help us around November. • FE Configuration ü Later. ü New FE boards are necessary. S. Nishida (KEK) Jul. 26, 2013 Merger Development Private Discussion 2

Data Flow Data format from FE boards (naïve idea; to be discussed) { record_length[7: 0], reserve[23: 0], eventno[31: 0], hitdata[575: 0] } • #bit for hitdata might increase (max 144× 8=1152) • eventno should be replaced to information from FTSW. • Possibility to include monitor information in data (variable length is OK? ) one event is sent at once phase? hck doesn’t stop S. Nishida (KEK) Jul. 26, 2013 Merger Development Private Discussion 3

Data Flow Receiver FIFO Data Merger Zero Suppress L 1 Buffer ……… ? Belle 2 Link S. Nishida (KEK) Jul. 26, 2013 Merger Development Private Discussion 4

Slow Control • Uchida-san’s SIO module (SIO_MASTER, SIO_SLAVE). • 32 bit address, 8 bit data • Same (similar) address map? Relation with Belle 2 Link Slow control? ASICのパラメータの設定や読 み出しに使うアドレス S. Nishida (KEK) Jul. 26, 2013 Merger Development Private Discussion 5

Backup S. Nishida (KEK) Jul. 26, 2013 Merger Development Private Discussion 6