Memristor Memory With Crossbar Architecture Naveen Murlimanohar HP
Memristor Memory With Crossbar Architecture Naveen Murlimanohar HP Labs June 14 th 2014 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Why New Technology? • Explosion of data – faster than Moore’s law − Memory is the focal point − Strong demand for cheap memory • In memory computation is gaining popularity − Volt DB, SAP HANA, Memcached • DRAM cost/bit is high and its scaling is slowing − DRAM is also volatile • Other technologies such as PCM and STT-RAM are facing challenges 2 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Technology Trend – Memory Scaling Problem • DRAM capacity increase 4 X / 3 years for decades, but now is scaling much slower Source: Horst Simon 3 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Memory Capacity • Requirement 1 B/FLOP Ref: DARPA’s exascale report By 2020 we could be well below <0. 1 B/FLOP! More number crunching with less data 4 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities 5 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
The memristor: 4 th fundamental two terminal circuit element v Ohm 1827 Predicted 1971 Leon Chua U. C. Berkeley 1831 Faraday RESISTOR dv = R di Reduced to practice 2008 R. Stanley Williams HP Laboratories Von Kleist 1745 CAPACITOR dq = C dv q i MEMRISTOR dφ = M dq INDUCTOR dφ = L di 1971 Chua φ 6 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Memristor - First Glance The memristor is built on a Metal-Insulator-Metal (MIM) structure. • Memristor can be switched between High Resistance State (HRS) and Low Resistance State (LRS) by applying an external voltage across the cell. • Current, voltage relationship is non-linear • 7 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Memristor Cell Ideally we want the memristor IV curve to be highly nonlinear Memristor Selector with high non-linearity Selector Memristor Cell Memristor switching device with low non-linearity Combination of a selector in series with memristor device 8 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Accessing Traditional Memory • 2 D grid of cells with a dedicated access switch in each cell • Easier to read/write to a cell • Low density but high read margin 9 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Traditional Memory vs. Memristor Crossbar Row select signal to read or write a row Cells being read or written 10 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Traditional Memory vs. Memristor Crossbar Access transistor isolates unnecessary signal - But it increases cost Cells being read or written 11 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Crossbar Memristor array Half Selected Cell • No access transistor a dense crossbar array with a cell size of 4 F 2 • You can lay transistors and circuits below the array • Maximum use of silicon area 12 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities 13 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Memristor Operation Vdd/2 Vdd/2 Vdd/2 HP Confidential 0 Vdd/2 Row select signal to read or write a row
Memristor Operation Vdd/2 Vdd/2 0 Vdd/2 Vdd Half Selected Cells Leak Current Vdd/2 Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2) HP Confidential
Memristor Operation Unselected cells shown in light blue will also get impacted Vdd/2 Vdd/2 0 Vdd/2 Vdd/2 Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2) HP Confidential
Complex Tradeoffs in Crossbar Write Array size V Read Enough voltage drop (for switching) Avoid write disturbance I? selected cell V/2? V/3? Floating? >1 bit? ? Enough ∆I (noise margin) HP Confidential
Complex Tradeoffs in Designing Memristor Crossbar • Design decisions are not obvious V • What is the optimal array dimensions? • What is the right driving voltage? • What is the biasing voltage? Enough voltage drop (for switching) Avoid write disturbance I? selected cell V/2? V/3? Floating? • Tradeoff in writing/reading single bit vs. multiple bits per array ? Depending upon the delay/energy/area constraints, we can tune the array accordingly HP Confidential Enough ∆I (noise margin)
Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities
Operating Voltage vs. Array Size Big array requires large voltage 20 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Choice of Material Maximum Number of Wordlines & Bitlines Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2) • Non-linearity increases the density 21 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Read Operation • The read voltage/current is lower than that of the write operation • The read reliability is determined by the voltage swing for reading HRS and LRS cells • However, sneak path and data pattern can reduce the voltage swing 22 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Operating Speed vs. Density vs. Bandwidth Larger array More sneak paths Lower read margin Challenging with process variation 23 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Two-Step Read Operation • Two-step sensing: senses the background current first, then the overall current is sensed • Increased sensing overhead low bandwidth or poor density 24 One-step Reading Two-step Reading © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities 25 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
More Challenges • Reliability of crossbar • Process variation • Fault tolerance • Data encoding 26 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
Effect of Data on Sneak Current Vdd/2 Vdd/2 0 Vdd/2 Vdd 1 0 0 Cells in low resistance state More sneak current HP Confidential Half Selected Cells Leak Current
Impact of data pattern Write the furthest cell in a 8 x 8 cross-point array # of “ 1”s (LRS) in the selected wordline matters gap between worst-case and best case? switching time (s) Votlage drop (m. V) 660 650 640 630 1 E-06 1 E-07 620 1 E-08 610 2 3 4 5 6 7 8 2 # of "1"s in selected wordlines worst-case best-case 3 4 HP Confidential 6 # of "1"s in selected wordlines worst-case 28 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. 5 best-case 7 8
Impact of data pattern Write the furthest cell in a 8 x 8 cross-point array positions of “ 1”s (LRS) in the selected wordline also matter moving “ 1”s closer to the write driver helps hints: mirror coding 1. 2 E-07 switching time (s) voltage drop (m. V) 660 656 652 1. 0 E-07 8. 0 E-08 Data in selected wordline 29 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential 10000001 01000001 001000010001 00001001 00000101 4. 0 E-08 00000011 648 00000011 6. 0 E-08
Summary • Opportunity to change the memory technology do not come along everyday • More aggressive micro architecture that can provide better density than existing technologies is critical • Memristor characteristics are well suited for future memory systems • Crossbar architecture is an interesting way to leverage resistive memories such as Memristor • Its high density along with architectural enhancements can make it a compelling option for future systems 30 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice. HP Confidential
Memristor. . . More Info. . . Resources – Learn more… Memristor Basic Info: The Memristor – Incredible: https: //www. youtube. com/watch? v=w. ZAHG 3 COYYA Wikipedia on Memristor: http: //en. wikipedia. org/wiki/Memristor Technical papers: • Niu et al. , Design of Cross-point Metal-oxide Re. RAM Emphasizing Reliability and Cost. ", (ICCAD), 2013. • Xu et al. , Understanding the Tradeoffs in MLC Re. RAM Memory Design, DAC, 2013. • Niu et al. , Design Tradeoffs for High Density Cross-Point Resistive Memory. ", ISLPED, 2012. 31 © Copyright 2013 Hewlett-Packard Development Company, L. P. The information contained herein is subject to change without notice.
The basic model of crossbar array Voltage controlled current source Memristor Selector Current controlled voltage source Vw/ V’w • VB / V’B • : Voltage at the edge of wordline : Voltage at the edge of bitline Rl : Interconnection wire resistance • Ri, j : Resistance of the memristor at the intersection of the ith wordline and the jth bitline • Vi, j / V’i, j : Top/bottom voltage of the memristor with Ri, j Array 2013 simulation is done. Company, through Hewlett-Packard Development L. P. The. HSPICE information contained herein is subject to change without notice. 32 • © Copyright •
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