MemoryDriven Computing The future of computing Presentation to

Memory-Driven Computing The future of computing Presentation to the Orlando chapter of INCOSE August 16 th, 2017 Ian Phillips, ESEP Principal Systems Architect Lockheed Martin EBS Ian. phillips@lmco. com

Agenda – Motivation for Memory Driven Compute – Challenges with memory with today’s computer systems – Introducing Gen-Z and architecture concepts – The Machine update ([--TB_Third_PARTY--]) Third Party Proprietary Information

What is the motivation? 3

The New Normal: Compute is not keeping up Log Scale Data growth (~ doubling every 2 years, exponential growth) Microprocessors 107 50 Transistors (thousands) 106 45 40 105 Single-thread Performance (Spec. INT) 104 Frequency (MHz) 103 [Y VALUE] 35 Data nearly doubles every two years (20132020) 30 101 Typical Power (Watts) 15 Number of Cores 10 5 100 1975 1980 1985 1990 1995 2000 2005 2010 2015 Start of CPU degradation trend [Y VALUE] 25 20 102 Data (Zettabytes) [Y VALUE] [Y [YVALUE] [Y [Y VALUE] 0. 3 VALUE] 0 2006 2008 2010 2012 2014 2016 2018 2020 End of CPU degradation trend End of Moore’s Law 4

Memory 5

Definitions –Memory – The physical media used to store the information required by a computer to execute programs – Directly addressable by the processor – All instructions and data operated on by a computer reside in, or pass through, memory (i. e. , the von Neumann architecture) –Volatile memory – Memory that loses its information when power is removed –Nonvolatile memory – Memory that retains its information when power is removed; accidentally, maliciously, or purposefully

Computer Processor Architecture – A classic, contemporary computer processor architecture Ø Memory is directly addressable by the processor So. C = System on Chip So. C DDR 7

Extending Computer Processors using standard integrations. Motherboard NVDIMM DDR ISA Slot VME Slot SATA So. C Slot USB Slot SCSI Slot PCIe Slot DDR – Computer Processors are integrated with a variety of media adapters using standard integrations such as ISA, VME, SATA, USB, SCSI, PCI, and many others. – These media adapters allow CPUs to integrate with a wide variety of peripheral devices including data storage devices, hardware integration adapters, networks and user interface devices. – These interfaces are all extremely inefficient at handling I/O when compared to CPU memory I/O. – Most Media peripherals operate with their own CPU/Compute, adding to the latency problem. 8

Convergence of Memory and Storage: Storage Class Memory In-Memory Operations X 5 Processor 1 ns X 20 SRAM 5 ns SCM Ops X 2000 DRAM 100 ns Block Operations X 50 Flash 200, 000 ns X 4000 Hard Drive 10, 000 ns Tape 40, 000, 000 ns • Byte Addressability • Data Protection methods (RAID, EC) • High Bandwidth/Low Latency • Device management: Hotplug-ability • Simple & Efficient Load/Store operations • Rich Data Services (ie deduplication, replication, thin provisioning, etc) 9

The “memory” hierarchy Level Register L 1 cache Amount Access time (approximate, in processor cycles) 1 2 L 2 cache 10 L 3 cache 60 Memory 300 SSDs 250, 000 Disk 7, 500, 000 Operation Energy (p. J) 64 -bit integer operation 1 64 -bit floating-point operation 20 256 bit on-die SRAM access 50 256 bit bus transfer (short) 26 256 bit bus transfer (1/2 die) 256 Off-die link (efficient) 500 256 bit bus transfer(across die) 1, 000 DRAM read/write (512 bits) 16, 000 HDD read/write (32 k bits) 10

Memory/Storage Convergence: The Media Revolution Today Memory DRAM OPM Internal Block Storage SCM Disk/SSD SCM = Storage Class Memory OPM = On-Package Memory Semantics will be pervasive in Volatile AND Non-Volatile Storage as these technologies continue to converge. 11

What are the Solution Elements? • Eliminate architectural bottlenecks by simplifying HW/SW interfaces • Speak the common language of CPU data access • Extend memory semantics to all devices • Design for highest data bandwidth, lowest latency to all devices • Flexible architecture that utilizes scalable technology for keeping up with the data growth trend • Reduce acquisition and operational costs 12

Ultra-fast HPE Persistent Memory Today Current Gen 10 Persistent Memory Products Large in-memory compute Checkpoints and Restores HTAP- Real Time Analytics Large Databases VSAN and Storage Spaces Direct Big Data, Service Providers, Performance Tier, and Virtualizations HPE NVDIMMs Database Storage Bottlenecks Software Licensing Reduction Caching - HPE 16 GB NVDIMMs Database Workloads 1 TB in 2 socket Small (100 s of GB) - Large (Terabytes) HPE Scalable Persistent Memory Industry leading persistent memory technology delivers performance, resiliency, scale and efficiency required of data intensive applications 13

Memory Semantic Fabric & the Gen-Z Consortium 14

Memory Semantic Fabric Communication at the speed of memory What is a Memory Semantic Fabric? • A communication protocol that speaks the same language the CPU speaks: load/store, put/get, and read/write • Memory address based connectivity that extends beyond the CPU to the server, to the rack and to the data center. CPUs So. C Memory Accelerators FPGA GPU Memory Semantic Fabric Pooled Memory Network Storage I/O 15

The Gen-Z Consortium: Broad Industry & Device Support http: //genzconsortium. org/ Component Categories Consortium Members Components IBM Power Intellectual Property CPUs GPUs Special Purpose Processors Connectors Subsystems Storage Controllers Switches/ Gateways PCM Systems FPGAs Re. RAM STTRAM HMC Software Memristor Volatile Memory 3 D XPoint Storage Class Memory 16

A high speed Gen-Z memory semantic fabric SCM Gen-Z Fabric SCM Media Controller SCM Gen-Z Logic Media Controller Gen-Z Logic Media Module So. C Media Module CPU SCM GPU or FPGA • Supports DRAM, Flash, Memristor, PCRAM, MRAM, 3 D XPoint … Universal Interconnect • Decouples CPU/memory design, enabling independent innovation CPU Media Module GPU or FPGA Media Module Media DRAM Media Controller Gen-Z Logic Gen-Z Fabric Gen-Z Switch Storage Class Memory Accelerator Module SCM Media Module So. C SCM SCM Media Controller So. C DRAM Media DRAM Multiple Resources Enabled by Gen-Z 17

Memory-Driven Computing 18

Memory Driven Computing (MDC) – Memory is the scarce compute resource • Conventional computers move date to a processor – MDC flips that around • Brings processing to the data • Processors handle individual tasks • Change processors to suit compute task – With this architecture, we can process massive datasets – Saves energy (multiple orders of magnitude) Memory Driven Computing technologies are not substitutional. Requires re-architecting the fundamentals of computer systems. 19

Memory Driven Computing (MDC) Memory Me ry o em mo C C So So. C Fabric C So C C So mo Me ry So. C Memory + So So. C C Memory y or Me m C mo Me y So. C Memory C So r mo C So So y C So So Me mo r So So. C Me C So So. C ry So. C M y or Me m ry Memory From processor-centric computing… …to Memory-Driven Computing 20

Gen-Z & HPE’s “The Machine” Gen-Z Photonics General / special purpose cores Massive common memory pool The Machine 21

MDC in context Physical Server So. C Local NVM Local DRAM Network Local DRAM So. C Local DRAM Local NVM Shared nothing So. C Physical Server So. C Local DRAM Shared something NVM So. C NVM Local DRAM Local NVM Coherent Interconnec t Local DRAM So. C Network Local NVM Network So. C Local DRAM Communications and memory fabric So. C Mainframe MDC Conventional Servers Local DRAM Local NVM Memory Pool Shared everything • All fabric attached resources shareable • Memory synchronization left to the application writers. • High performance data sharing mechanisms available 22

So. C Memory Access Memory Semantic Fabric 2 -4 TB So. C Bridge “Private” memory Universal Memory So. C “Private” memory Bridge Universal Memory

HPE’s “The Machine” with 160 TB Memory 24

HPE’s “The Machine” Architecture 25

Installing a Node 26

HPE’s The Machine: Memory fabric testbed Machine Board Powerful Open A quantum leap in performance, beyond what you can imagine An open architecture designed to foster a vibrant innovation ecosystem Trusted Simple Always safe, always recoverable All the benefits without asking for sacrifice Structurally simple, manageable and automatic, so that “it just works” 27

“The Machine” prototype specification and architecture specs • The Machine Prototype 160 TB of memory • Each enclosure has 10 nodes, 4 enclosures in prototype, total of 40 nodes • Each node has a fabric-attached memory board with 4 TB • Each Node has 1 So. C • HPE’s Memory-Driven Computing is the foundation for high-performance compute for data intensive workloads, including big data analytics. • Exascale High Performance Computing (HPC) initiative aims to create single systems with more computational power than the current top 500 supercomputers combined. • Petascale systems for commercial enterprise applications, capable of analyzing petabytes of data in memory. Six “The Machine” prototypes would provide a petascale system! • Exascale systems for supercomputing applications, capable of analyzing exabytes of data in memory • Architecture scales from tiny Io. T devices to exascale computers Typical Server 1 TB RAM X 1000 Petascale System 1 PB Memory X 1000 Exaascale System 1 EB Memory Petascale is 1 Million Gigabytes memory Exascale is 1 Billion Gigabytes memory 28

Photonics 29

Photonics: Light inside “The Machine” • “The Machine” prototype moves fiber optics cables inside the computer for internal data transmission • Copper currently runs at 5 gigabits per second (gb/s) • Copper can only go to 9. 6 gb/s. • Optical connections will go to at least 20 gb/s • Maybe as high as 6 terabytes/sec • Photonic data access will address any one byte of data in a 160 petabyte online data store in under 250 nanoseconds (a nanosecond is one billionth of a second). • Optical connections also use much less power. Specific savings ratios are configuration dependent. 30

Memristor 31

Memristor Memory Technology v q I ᴪ • Power used by memristor is tiny • Power required to write is low • No power needed after write • Once programmed, the state is absolutely stable • • • Non-volatile Fast Dense Low energy Stable • A memristor is of a two-terminal device whose resistance depends on the magnitude, polarity and time of the applied voltage. • When the voltage is turned off, the resistance remains as it was when turned off. • This makes the memristor a non-linear, nonvolatile memory device.

Hardware + software stack Insight Analytics and visualization Exabyte-scale algorithms Manageability Operating systems and programming models Data Security built on HW foundations >_ Ultra-efficient hardware Linux for The Machine will be Open Source 33

Applications 34

Transform performance with Memory-Driven programming Modify existing frameworks Completely rethink New algorithms 15 X 100 X 300 X 8000 X faster In-memory analytics Large-scale graph inference Similarity Search Financial models

Graph analytics time machine Massive memory and fast fabrics to ingest all data “Are there any emerging new behaviors in my network? ” Critical node Remote users External users Fast graph databases and the ability to look at things that change over time 36