Memory Storage Architecture Lab Seoul National University Flash

Memory & Storage Architecture Lab. @ Seoul National University Flash. Tier: A Lightweight, Consistent and Durable Storage Cache Mohit Saxena, Michael M. Swift and Yiying Zhang (University of Wisconsin-Madison) Proceedings of the 7 th ACM european conference on Computer Systems (Euro. Sys’ 12) July 25, 2013 발표: Jeong Su Park (jspark@archi. snu. ac. kr) School of Computer Science and Engineering Seoul National University

SSD as a cache Host OS DRAM Cache manager - Cheaper than DRAM - Improve cold start performance (Non-volatile nature) SSD - Faster than HDD Memory & Storage Architecture Lab. @ Seoul National University 2

Drawbacks of conventional SSD as a cache SSD address space (LBA-s) Host OS HDD LBA-d to LBA-s Mapping info Cache manager SSD HDD address space (LBA-d) 1. 2. 3. Consumes a lot of DRAM resources Should guarantees consistency & durability of mapping info Garbage collection degrades performance HDD Memory & Storage Architecture Lab. @ Seoul National University 3

Solid State Cache (SSC) SSC address space (Same as LBA-d) Host OS HDD LBA-d to LBA-s Mapping info < Flash. Tier > Cache manager SSC HDD address space (LBA-d) 1. 2. 3. HDD Unified address space -> Remove mapping info (DRAM resource save) Interface expansion -> Garbage collection overhead reduction (Performance enhancement) Consistency & durability guarantee with checkpoint & roll-forward (Fast crash recovery) Memory & Storage Architecture Lab. @ Seoul National University 4

Unified address space < General purpose SSD > Cache manager LBA-d to LBA-s SSD 1. Request 2. Request (Miss) SSD address space (LBA-s) 2. Result (Hit/Miss) SSC LBA-s to PA HDD address space (LBA-d) Memory & Storage Architecture Lab. 3. If missed Same as LBA-d to PA (Physical Address) @ Seoul National University LBA-d to LBA-s Cache manager 1. Look-up 2. Request (Hit) < Solid State Cache > HDD address space (LBA-d) 5

Interface expansion Physical blocks Clean Meta info Invalid LBA-d to PA Block info (Liveness/ Data status) 1. Write-through policy Choose victim (all clean | invalid) and erase only when remaining free blocks are insufficient (Silent-evict) Write-clean Clean-data Cache manager Read Hit/miss SSC Clean-data HDD Read Always hit Clean-data Memory & Storage Architecture Lab. @ Seoul National University 6

Interface expansion Physical blocks Clean Meta info LBA-d to PA Block info (Liveness/ Data status) 2. Write-back policy Invalid Dirty Erasure is not permitted Choose victim (all clean | invalid) and erase only when remaining free blocks are insufficient (Silent-evict) Write-dirty Dirty-data Cache manager Read Hit/miss SSC HDD Read Always hit Memory & Storage Architecture Lab. @ Seoul National University 7

Interface expansion Physical blocks Clean Invalid Meta info LBA-d to PA 2. Write-back policy - Clean : SSC mapping info preserved until silent-evict occurs - Evict : SSC mapping info vanishes immediatly Dirty Block info (Liveness/ Data status) Choose victim (all clean | invalid) and erase only when remaining free blocks are insufficient (Silent-evict) Clean or evict Dirty block table LBA-d Cache manager SSC clean evict HDD Dirty-data Memory & Storage Architecture Lab. @ Seoul National University Dirty-data 8

Interface expansion / crash recovery Physical blocks (Checkpoint area) Meta info LBA-d to PA Block info (Liveness/ Data status) Periodically checkpoint entire set with seq. # Physical blocks (Logging area) 2. Write-back policy Logging updated portion with seq. # Dirty block table re-construction with ‘exist’ query During crash recovery Exists Dirty block table LBA-d range Cache manager Dirty data status within queried range Memory & Storage Architecture Lab. @ Seoul National University SSC Restore most-recent checkpoint info & roll-forward logging area during crash recovery 9

Evaluation (write intensive) SSD (read intensive) Flash. Cache Flash. Simulator Vs. Trace replay Linux kernel 2. 6. 33 SSC (fixed page-mapped area) SSC-R (flexible page-mapped area) Cache manager (Modified Flash. Cache @ Facebook) Modified Flash. Simulator + Custom Hybrid mapping FTL ※ Hardware implementation M. Saxena, Y. Zhang, M. M. Swift, A. C. Arpaci Dusseau, and R. H. Arpaci Dusseau, “Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems, ” FAST 13. Memory & Storage Architecture Lab. @ Seoul National University 10

Results Write intensive Read intensive Proposed device Proposed cache manager Native : Host should reconstruct entire mapping info. before running => Entire storage area scan needed (mapping info. is stored in spare area) Proposed : Host may defer reconstructing dirty block info. + dirty block info. can be quickly reconstructed from checkpoint & roll-forward. (Not fair…. ) Memory & Storage Architecture Lab. @ Seoul National University 11

Results Memory & Storage Architecture Lab. @ Seoul National University 12