Memory Organization 1 MEMORY ORGANIZATION Memory Hierarchy Main

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Memory Organization 1 MEMORY ORGANIZATION • Memory Hierarchy • Main Memory • Auxiliary Memory

Memory Organization 1 MEMORY ORGANIZATION • Memory Hierarchy • Main Memory • Auxiliary Memory • Associative Memory • Cache Memory • Virtual Memory • Memory Management Hardware Computer Organization Computer Architectures Lab

Memory Organization 2 Memory Hierarchy MEMORY HIERARCHY Memory Hierarchy is to obtain the highest

Memory Organization 2 Memory Hierarchy MEMORY HIERARCHY Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system Auxiliary memory Magnetic tapes I/O processor Main memory CPU Cache memory Magnetic disks Register Cache Main Memory Magnetic Disk Magnetic Tape Computer Organization Computer Architectures Lab

Memory Organization 3 Main Memory MAIN MEMORY RAM and ROM Chips Typical RAM chip

Memory Organization 3 Main Memory MAIN MEMORY RAM and ROM Chips Typical RAM chip Chip select 1 Chip select 2 Read Write 7 -bit address CS 1 CS 2 0 0 0 1 1 0 1 0 1 1 CS 2 RD WR AD 7 RD x x 0 0 1 x WR x x 0 1 x x 128 x 8 RAM 8 -bit data bus Memory function Inhibit Write Read Inhibit State of data bus High-impedence Input data to RAM Output data from RAM High-impedence Typical ROM chip Chip select 1 Chip select 2 9 -bit address Computer Organization CS 1 CS 2 512 x 8 ROM 8 -bit data bus AD 9 Computer Architectures Lab

Memory Organization 4 Main Memory MEMORY ADDRESS MAP Address space assignment to each memory

Memory Organization 4 Main Memory MEMORY ADDRESS MAP Address space assignment to each memory chip Example: 512 bytes RAM and 512 bytes ROM Component RAM RAM ROM 1 2 3 4 Hexa address 0000 - 007 F 0080 - 00 FF 0100 - 017 F 0180 - 01 FF 0200 - 03 FF Address bus 10 9 0 0 1 1 x 8 7 6 5 4 3 2 1 0 1 x x x x x x x x x Memory Connection to CPU - RAM and ROM chips are connected to a CPU through the data and address buses - The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a particular chip through its chip select inputs Computer Organization Computer Architectures Lab

Memory Organization 5 Main Memory CONNECTION OF MEMORY TO CPU CS 1 CS 2

Memory Organization 5 Main Memory CONNECTION OF MEMORY TO CPU CS 1 CS 2 128 x 8 RD RAM 2 WR AD 7 CS 1 CS 2 128 x 8 RD RAM 3 WR AD 7 CS 1 CS 2 128 x 8 RD RAM 4 WR AD 7 1 - 7 8 9 Computer Organization CS 1 CS 2 512 x 8 AD 9 ROM Data CS 1 CS 2 128 x 8 RD RAM 1 WR AD 7 Data Decoder 3 2 1 0 Data bus Data RD WR Data 7 -1 Data Address bus 16 -11 10 9 8 Computer Architectures Lab