Memory Mapped IO Section 8 5 Appendix A

Memory Mapped I/O Section 8. 5, Appendix A. 8. Bus keyboard monitor Processor mouse printer Assembly line robot controller Funny device How should the processor control & communicate with the I/O devices?

I/O Processor Control Interface What kind of control/data need be transferred? Keyboard: processor keyboard: data ready? read-data? keyboard processor: data ready Printer: processor printer: data-sent print font, resolution? printer processor: printing done. error conditions – out of paper, toner

I/O Processor Control Interface contd. Assembly-line robot: processor robot: move (direction, amount) action: grab, tighten robot processor: error- obstacle, diagnostics Hard disk: processor disk: seek sector seek track read/write block disk processor: data-ready error conditions – bad block

I/O Processor Control Interface contd. Should we include instructions for these control tasks? Is there enough uniformity between I/O devices to agree on a single set of instructions to communicate with them? How about the I/O devices we have not even foreseen yet? Hard to develop an instruction set to control today’s and tomorrow’s devices!

Memory-Mapped I/O Contd. Make the interface between the I/O device & processor soft. Let it be developed as a data structure. Control Data An I/O handler, a program that uses these data structures to coordinate the control and data transfer. Where does this control/data structure reside?

Memory-Mapped I/O Contd. I/O 0 xffff 0 x 7 fffffff Stack Dynamic data Memory-mapped I/O Static data 0 x 10000000 Text/Program OS The control and data registers are mapped in the memory. 0 x 400000

Keyboard example processor Keyboard Data register Control register R getchar(): reads an ASCII byte from keyboard and deposits it in $v 0. 0 x 7 fffffff $s 0 0 x 7 fffffff 0 x 81111114 poll: lw $t 0, 4($s 0) andi $t 0, 0 x 1 beq $t 0, $zero, poll getchar: move $v 0, 0($s 0) ?

How Does Keyboard Know It’s Memory Map? #Bytes (256) Chip-Select 0 (CS 0) CS Base(0 xf 0000000) processor Keyboard Chip Enable Data register Control register R 0 xf 0000000 0 xf 0000004

Polling some synchronization flag repeatedly until flag is true. Producer Shared Lock resource Consumer Is it efficient to poll? Sometimes yes, sometimes no!

Polling Overhead Device Data Rate Keyboard Mouse Scanner Line printer 100 B/s 200 B/s 400 KB-1 MB/s 1 KB/s Laser printer Video monitor Network card Modem Floppy disk 200 KB-. 5 MB/s 50 MB-1 GB/s 1 MB-100 MB/s 2 KB-8 KB/s 100 KB/s 1600 X 1200 pixels/fr 7. 68 Mpixels/Fr 2 B/Pixel 15. 36 MB/Fr 60 Fr/s 921. 6 MB/s Interlaced 30 Fr/s: 460. 8 MB/s

Polling overhead contd. Polling overhead: 600 cycles transfer to polling procedure, access the device, return to the user program. CPU: 1 GHz Fraction of CPU time spent polling? : mouse: must be polled at least 30 times/s Polling clock cycles: 30 polls/s * 600 c/poll = 18000 c/s CPU clock cycles/s: 109 c/s Polling overhead: (18000)/(109)=18*10 -4% =. 0018%

Polling overhead contd. Fraction of CPU time spent polling? : floppy disk: transfers in 2 B units at a data rate of 100 KB/s. Polling rate? : (100 KB/s)/(2 B/poll) = 50 K polls/s Polling clock cycles: 50 K polls/s * 600 c/poll = 30 M c/s CPU clock cycles/s: 109 c/s Polling overhead: (3*107)/(109)=. 03 = 3%

Polling overhead contd. Fraction of CPU time spent polling? : network card: transfers in 8 B units at a data rate of 10 MB/s. Polling rate? : (10 MB/s)/(8 B/poll) = 1. 25 M polls/s Polling clock cycles: 1. 25 M polls/s * 600 c/poll = 750 M c/s CPU clock cycles/s: 109 c/s Polling overhead: (75*107)/(109)=. 75 = 75%

Polling overhead contd. Fraction of CPU time spent polling? : video monitor: transfers in 16 B units at a data rate of 320 MB/s. Polling rate? : (320 MB/s)/(16 B/poll) = 20 M polls/s Polling clock cycles: 20 M polls/s * 600 c/poll = 12 G c/s CPU clock cycles/s: 109 c/s Polling overhead: (12*109)/(109)=12 = 1200%

Alternative to Polling Producer wakes up the consumer! Interrupts / Exceptions: term used in computer architecture. Exceptions/interrupts can be external or internal. Keyboard interrupts the processor to indicate that the data is ready. External --- interrupts. Internal exceptions: divide by zero, arithmetic overflow, data alignment error. Internal --- exceptions.

Why Interrupt I/O? Polling is what we have seen: main () { while(1) { Poll. Keyboard(); } If the program has tasks to do: main () { task 1(); Poll. Keyboard(); task 2(); Poll. Keyboard(); … } How to poll keyboard: Overhead: n Read port to see if a key is n Overhead = Polling pressed frequency × Polling n Must poll every n ms, the overhead minimal time period a key Ease of programming: is pressed; otherwise user n Hard to mix polling with a keystroke is lost. normal process

Interrupt-Based C Programming char input_buffer[1024]; main() { set_interrupt_handler(); task 1(); task 2(); /* process buffered input */ read_user_input(); // more tasks } void interrupt_handler(int type) { Poll. Keyboard(); … /* write to input_buffer */ } Details are platform-dependent n n Desktop systems: OS manages all interrupts, put into buffers; or send signal to application programs Embedded systems: applications handle interrupts

Normal Control Flow In a processor, the program counter (PC) takes a sequence of values a 0, a 1, …, an-2, an-1 where each ak is the address of an instruction Ik. n n Control transfer: each transition from ak to ak+1 Flow of control, or control flow: sequence of control transfers “Smooth” control flow: Ik and Ik+1 are adjacent in memory Changes to smooth flow: Ik+1 not adjacent to Ik n n Branches Calls, returns

Exceptional Control Flow Exceptional control flow (ECF) Abrupt changes in control flow not caused by program statements and variables: Ik+1 is external to the program n n n n Hardware timer goes off at regular intervals I/O request completes, e. g. , A/D conversion, disk I/O Packets arrive at network adapter Instruction attempts divide by zero Arithmetic overflow occurs Virtual memory page fault occurs Memory access violation Occurs at all levels in a computer system: hardware,

Exceptions n n n form of ECF implementation details vary from system to system DEFINITION: an abrupt change in the control flow in response to some change in the processor’s state n n Event: change in processor’s state, where state is encoded in various bits and signals inside the processor Event might be related or unrelated to current instruction User program Event occurs here Icurr Inext Exception handler Exception return (optional) Exception processing

Classes of Exceptions Four classes of exceptions: 1. 2. 3. 4. Class Interrupts Traps Faults Aborts Cause A/S Return behavior Interrupt Signal from I/O device Async Always returns to next instruction Trap Intentional exception Sync Always returns to next instruction Fault Potentially recoverable error Sync Might return to current instruction Abort Nonrecoverable error Sync Never returns

Exception processing n n n How is an exception signaled? How is the desired exception service indicated? How does the processor prioritize and accept exceptions? How is the control transferred from the interrupted program to the exception service? How is the interrupted program resumed?

Exception processing: Exception signaling Internal exception: who initiates the exception? who needs to know that an exception has occurred? Processor controller needs to be aware of an exception. Exceptions are generated by instructions: Arithmetic overflow Illegal instruction Data alignment error

Exception processing: Exception signaling Contd. External interrupt: Interrupts generated by external devices such as keyboard & mouse? IRQ: interrupt request Processor

Exception processing: Exception signaling Contd. Level 1 Processor I 0 I 1 I 2 Level 3 Priority encoder Level 4 Level 5 Level 6 000: no interrupt 010: level 2 int. Level 7

Exception processing: Exception Service How can an exception service be specified? What is an exception service? A robot? A mechanical service? A procedure (program): its address specifies the desired service. Typically called ISP (interrupt service procedure). Two General Mechanisms: (1) Centralized dispatch: exception handler decodes (2) the cause. (MIPS style) (3)(2) Vectored dispatch: the hardware based on (4) a vector number invokes the appropriate service. (5) (Power. PC style)

Exception processing: Exception Service Contd. PC: 0 x 80000180 PC: 0 x 80000080 Exception handler 0 x 80000080 add $t 0, $t 1 div $t 0, $t 3 mfhi $t 2 addi $t 2, 1

Exception Handler if (cause == Arithmetic Overflow) Arithmetic. Overflow. Handler(); else if (cause == Divide. By. Zero) Divide. By. Zero. Handler(); else if (cause == Illegal Instruction) Illegal. Instruction. Handler(); else if (cause == external interrupt) Interrupt. Handler(); ----Cause Register Cause code 00

Cause Register Pending interrupts IP 5 IP 4 IP 3 IP 2 IP 1 IP 0 SW 1 SW 0 Part of conceptual co-processor 0 mfc 0 $t 0, $13 or mfc 0 $t 0, $cause 00 4 Cause code 00 0 Ext. interrupt 4 Load addr. error 5 Store addr. error 11 CPU 12 Overflow

Vectored Interrupts: Motorola Each exception & interrupt has a 8 -bit vector #: 0 -255 (for Motorola 68 xxx family) Vector# ISP address 4 byte 1 2 3 4 5 6 System reset Data addr error Inst addr error Ext. interrupt Alignment error C System call Starting address of ISP = vector#*4 + starting address of vector table = 0 x 1000 + 3*4 (for data addr error).

Vectored Interrupts: PPC maintains an exception vector table. Only 32 vectors available. Each vector is given 100 words of space in exception vector table. A primitive ISP goes in that space. Vector 0 Vector 1 Vector 2 Vector 31 Addr: 0 x 00000100 Addr: 0 x 00000200 Addr: 0 x 00001 f 00

Exception processing: prioritization If multiple exceptions/interrupts raised simultaneously, how do we prioritize them? In general: internal exceptions (software raised) are always given higher priority than the external interrupts (hardware device initiated). Within software exceptions, there might be multiple levels of prioritization: 2 in MIPS. Within external interrupts, multiple levels of priority: 6 in MIPS.

Exception processing: prioritization contd. Cause Register Pending interrupts IP 5 IP 4 IP 3 IP 2 IP 1 IP 0 SW 1 SW 0 00 4 Cause code 00 Look at all the pending interrupts at the entry into the exception-handler. If more than one is 1, choose based on the priority. Can a higher priority interrupt pre-empt the ISP for a lower priority interrupt? There can be nested exception service procedures!

Exception processing: Control transfer v. Exception-handler is just like any other procedure. v. Calling is not done through a procedure call. v. It is called by the processor controller by forcing its address 0 x 80000080 into PC. What should be saved before forcing 0 x 80000080 into PC (so that we can resume the interrupted program)? Current program’s state including its address.

Exception processing: Control transfer Contd. Right before PC 0 x 80000080, the current PC is saved in EPC: PC EPC (Exception PC). EPC is Reg. 14 in co-processor 0: mfc 0 $t 0, $14 or mfc 0 $t 0, $EPC Other program state is kept in Status Register: K/U I. E. 15 Interrupt mask 8

Exception processing: Control transfer Contd. While in exception-handler, can another exception be accepted? EPC gets overwritten similar to $ra! One of the first acts in exception-handler should be to save EPC, cause, and status register on a stack. While saving these registers, should we disable all the interrupts?

Exception processing: Control transfer Contd. K/U I. E. At entry into exception-handler: 0 0 (1) All exceptions are disabled. (2) K/U=0: kernel mode (supervisor mode). old prev. current K/UI. E. K/U I. E. 0 0

Exception processing: Control transfer Contd. exception-handler: exception-handler() mfc 0 $k 0, $cause { mfc 0 $k 1, $EPC /* keep the interrupts disabled */ sw $k 0, -4($sp) (1) save EPC, cause, status regs on sw $k 1, -8($sp) system stack. sw $t 0, -12($sp) (2) enable interrupts. (3) decode cause and call appropriate addi $sp, -12 mfc 0 $t 0, $status ISP. ori $t 0, 0 x 1 } mtc 0 $status, $t 0 andi $k 0, 0 x 3 c beq $k 0, $zero, interrupt -----

Exception processing: Control transfer PPC Machine State Register (MSR) 0 EE PR PR=0: supervisor =1: user EE=ext. interrupt enable =0: disable =1: enable RI=1: recoverable 0 IP IR DR 0 0 RI LE IP=0: exception Vector table LE=0 Starts at Big-endian 0 x 000 else 0 xfff

PPC Exception Registers Machine Status Save/Restore Register 0 (SRR 0) PC saved here Machine Status Save/Restore Register 1 (SRR 1) Exception specific info Save MSR bits 000000 1 -4 10 -15 E P E R MSR I P R L I E

PPC Exception Registers On an exception: IL E P E E R I P 00 R L I E 0 MSR mtmsr r 2: r 2 MSR mfmsr r 3: MSR r 3 mtspr SRR 0, r 2: r 2 SRR 0 mfspr r 3, SRR 1: SRR 1 r 3 Each exception handler must save SRR 0, SRR 1, and MSR before enabling exceptions (EE=1).

PPC Exception Priorities Non-maskable, asynchronous: Priority 1: System reset Priority 2: Machine check Synchronous, maskable: instruction dependent ones such as alignment, FP: Priority 3, 4. Asynchronous, maskable: external interrupt (priority 5) decrementer (priority 6).

Exception processing: resume Need to return from the exception handler to the interrupted program. Should we just use jr EPC? A special instruction: rfe return from exception. only restores the status register. K/UI. E. K/U I. E. EPC PC: need to use jr explicitly.

Exception processing: PPC resume return from interrupt: rfi. MSR[16 -23, 25 -27, 30 -31] SRR 1[16 -23, 25 -27, 30 -31] PC SRR 0[0 -29]||00

Interrupt Driven Keyboard IRQ processor Keyboard Data register Control register R ISP: getchar: lw $v 0, 0($s 0) jr $ra 0 x 7 fffffff 0 x 81111114

Interrupt-Handler IP 5 IP 4 IP 3 IP 2 IP 1 IP 0 SW 1 SW 0 exception-handler() { if (cause == interrupt at level 1) getchar(); } exception-handler: mfc 0 $k 0, $cause mfc 0 $k 1, $EPC sw $k 0, -4($sp) sw $k 1, -8($sp) sw $t 0, -12($sp) addi $sp, -12 mfc 0 $t 0, $status ori $t 0, 0 x 1 mtc 0 $status, $t 0 andi $t 0, $k 0, 0 x 3 c bne $t 0, $zero, noninterrupt 00 Cause code andi $t 0, $k 0, 0 x 800 beq $t 0, $zero, otherinterrupt jal getchar otherinterrupt: -----noninterrupt: -----rfe jr $k 1 00

Interrupt-Handler A-35, HP IP 5 IP 4 IP 3 IP 2 IP 1 IP 0 SW 1 SW 0 . ktext 0 x 80000080 sw $a 0, save 0 sw $a 1, save 1 mfc 0 $k 0, $13 #cause mfc 0 $k 1, $14 #EPC sgt $v 0, $k 0, 0 x 44 bgtz $v 0, done move $a 0, $k 0 move $a 1, $k 1 jal print_excp 00 Cause code 0000 00 done: lw $a 0, save 0 lw $a 1, save 1 addiu $k 1, 4 rfe jr $k 1. kdata save 0: . word 0 save 1: . word 0

Transmitter Control The character typed at the keyboard is echoed back to the keyboard (and displayed). IRQ processor lw $t 0, 0($s 0) ori $t 0, 0 x 2 sw $t 0, 0($s 0) #enables interrupt Keyboard Rec. Data register Rec. Control reg. IE R 0 x 7 fffffff 0 x 81111114 Trans. Data Reg. Trans. Control Reg. IE R 0 x 81111118 0 x 8111111 c

MIPS-32 Exception handling Cause register BD IP 5 IP 4 IP 3 IP 2 IP 1 IP 0 SW 1 SW 0 Cause code 00 00 BD=1: an instruction in the branch delay slot caused this exception. Status Register 15 Interrupt mask 8 K/U 00 EXL I. E. Exception level

MIPS-32 Interrupt-Handler. ktext 0 x 80000180 sw $a 0, save 0 sw $a 1, save 1 mfc 0 $k 0, $13 #cause srl $a 0, $k 0, 2 andi $a 0, 0 xf bgtz $a 0, done move $a 0, $k 0 mfc 0 $a 1, $14 jal print_excp done: mtc 0 $0, $13 mfc 0 $k 0, $12 andi $k 0, 0 xfffd ori $k 0, 0 x 1 mtc 0 $k 0, $12 lw $a 0, save 0 lw $a 1, save 1 addiu $k 1, 4 eret. kdata save 0: . word 0 save 1: . word 0