Memory and Programmable Logic Mano Ciletti Chapter 7

Memory and Programmable Logic Mano & Ciletti Chapter 7 By Suleyman TOSUN Ankara University

Outline n n n RAM Memory decoding Error detection and correction ROM Programmable Logic Array (PLA) Programmable Array Logic (PAL)

Memories n Memory unit is a collection of cells capable of storing a large quantity of binary information. q q n Information from input device is stored in memory Information to output is taken from memory Two types of memories q Random-access memory (RAM) n n n q Stores binary info for later use Write operation: Storing data into memory Read operation: Transferring data out of memory Read-only memory (ROM) n Can perform only read operation

RAM vs ROM n ROM is a programmable logic device (PLD). q n Other programmable devices q q q n The binary information is embedded within the hardware. Programmable logic array (PLA) Programmable array logic (PAL) Field programmable gate array (FPGA) Since PLDs have a lot of gates and paths, gates in array logic is shown in different way.

Random-Access Memory (RAM) n The time it takes to transfer to or from any random location always the same q q That’s why the name random access memory. In magnetic tapes, the time depends on the location of the data.

Word size n n n 4 bits - nibble 8 bits - byte 16 bits – 2 bytes 32 bits – 4 bytes Most computer uses multiples of 8 bits The capacity of a memory is stated as the total number of bytes.

A memory unit n Communication between memory and its environment is achieved by q q q Data input and output lines Address selection lines Control lines

Address n Each word is assigned to an address q n n Ranges from 0 to 2 k-1, where k is the number of address lines Internal decoder decodes the address for specific word. Memory size vs address lines q q 10 bits (k=10) can address 210 words 32 bits, 232 words

Memory addressing n A memory with 1 K words of 16 bits each

Read and Write Operations To read data n q q Put the binary address on the address lines Activate read input To write data n q q q Put binary address on the address lines Put data on data input lines Activate write input

Write cycle

Read cycle

Types of memories n Static RAM (SRAM) q q n Consists of latches to store binary data Stored data is valid as long as power is applied Easier to use Shorter write and read cycles Dynamic RAM (DRAM) q q Stores data in the form of electric charges on capacitors (MOS transistors). It must be refreshed periodically. Has less power consumption Larger storage capacity.

Volatile vs Nonvolatile n SRAMs and DRAMs are volatile memories q n Since they loose data when power is turned off Magnetic disks are nonvolatile q They store data using magnetization.

Memory Decoding n n n Decoders are used to select word locations. A memory with m words and n bits per word requires mxn storage cells. A basic cell is behaves like D latch (4 to 6 transistors) q q When read/write=1, read operation When read/write=0, write operation

4 x 4 RAM n n 4 words needs 2 address lines to be decoded 2 k words needs k address lines

Coincident decoding n A decoder with k inputs and 2 k output requires 2 k AND gates with k inputs per gate. q q Use two decoders to reduce this (two dimensional decoding) Two decoders with k/2 inputs 2 x 32=64 AND gates instead of 1024 AND gates (for 10 bits) 32 x 32 memory cell array

Error Detection and Correction n Error detection q n Use parity bits Error correction q q q Use multiple parity bits Each parity is generated for a group of bits If check parity bits are correct n q No error If check bit/bits are not correct n They give a pattern (called syndrome) that gives which bit is incorrect.

Hamming Code n K parity bits are added to n bit data q q q n Bit positions are numbered from 1 to n+k (no 0) Parity bits are positioned as powers of 2. Remaining bits are data bits. Example: data word is 11000100 (8 bit)

Parity generation

Parity check n n n C=C 8 C 4 C 2 C 1 If C=0, no error If C!=0, error (C gives the erroneous bit position)

Single error correction, Double error detection n Add additional parity bit (P 13)

ROM n n n Only read occurs K inputs and n outputs Nonvolatile

32 x 8 bit ROM n n 32 words of 8 bits each. 2 kxn ROM has kx 2 k decoder and n OR gates

Combinational Circuit Implementation n Similar to design procedure of circuits with decoders and OR gates as we have seen in Chapter 4. q We have decoders and OR gates inside of the ROM.

Design example n n B 1=0 B 0=A 0

Types of ROMs n ROM-mask programming q n PROM (programmable ROM) q n Can be programmed in a lab by blowing the fuses (all fuses initially intact) EPROM (Erasable PROM) q n Fill out the truth table, manufacturer makes the mask to produce 0’s and 1’s. Program it then erase under ultraviolet light. EEPROM or E 2 PROM(Electrically erasable PROM) q Can be programmed and erased electrically.

Combinational PLDs

Programmable Logic Array n n Similar to PROMS except that decoder is replaced with AND gates are connected to OR gates to produce sum-of-product terms.

An example PLA circuit n n F 1=AB’+AC+A’BC’ F 2=(AC+BC)’

Fuse Map n n n - means not connected, 1 means connected, 0 means complement is connected. T means true (for XOR) C means complement (for XOR)

Example

Programmable Array Logic (PAL) n n Fixed OR array and programm able AND array. Figure shows 4 input 4 output PAL

Design example n PALs may need simplifications as z includes w in this example.

Sequential Programmable Devices n n Needs flip-flops Types

SPLD

Basic Macrocell Logic