Memory and IO subsystem Reference Introduction to Digital

Memory and I/O subsystem Reference: Introduction to Digital System by Ercegovac, Lang & Moreno, Wiley Publisher 10/25/2021

Basic components of a computer • PROCESSOR; • MEMORY SUBSYSTEM; • INPUT/OUTPUT (I/O) SUBSYSTEM 10/25/2021

Memory hierarchy 10/25/2021

Specification of a simple processor System 10/25/2021

Memory Subsystem 10/25/2021

Entity Declaration of memory Subsystem LIBRARY ieee; USE ieee. std_logic_1164. all; USE WORK. comp_pkg. ALL; ENTITY Memory IS PORT (Addr : IN MAddr. T ; -- memory address bus Length : IN STD_LOGIC; -- byte/word operand Rd, Wr : IN STD_LOGIC; -- access control signals Enable : IN STD_LOGIC; -- enable signal Rdy : OUT STD_LOGIC; -- access completion signal Data : INOUT Word. T ); -- memory data bus END Memory; 10/25/2021

I/O subsystem 10/25/2021

Entity Declaration of I/O subsystem LIBRARY ieee; USE ieee. std_logic_1164. all; USE WORK. comp_pkg. ALL; ENTITY IO IS PORT (Addr : IN IOAddr. T ; -- I/O address bus Length : IN STD_LOGIC; -- byte/word control Rd, Wr : IN STD_LOGIC; -- I/O access control Enable : IN STD_LOGIC; -- I/O enable control Rdy : OUT STD_LOGIC; -- I/O completion signal Data : INOUT Word. T ); -- I/O data bus END IO; 10/25/2021

PROCESSOR • Processor state • 32 general-purpose registers (32 -bits wide), called R 0, R 1, . . . , R 31; • a 24 -bit Program Counter register (PC); • a 4 -bit Condition Register (CR); and • a 32 -bit Instruction Register (IR). 10/25/2021

Processor State 10/25/2021

Behavior of Processor 10/25/2021

Behavior of Instruction 10/25/2021

INSTRUCTION SEQUENCING • SEQUENTIAL UNLESS – 1. UNCONDITIONAL BRANCH – 2. CONDITIONAL BRANCH 10/25/2021

Instruction Format 10/25/2021

Instruction Set 10/25/2021

Instruction set (cont. ) 10/25/2021

Instruction set (cont. ) 10/25/2021