Manufacturing Process EE 141 1 Introduction What is

Manufacturing Process EE 141 1 Introduction

What is a Semiconductor? l l l Low resistivity => “conductor” High resistivity => “insulator” Intermediate resistivity => “semiconductor” l l conductivity lies between that of conductors and insulators generally crystalline in structure for IC devices l In recent years, however, non-crystalline semiconductors have become commercially very important polycrystalline amorphous crystalline EE 141 2

Semiconductor Materials Phosphorus (P) Gallium (Ga) EE 141 3

Silicon l l Si has four valence electrons. Therefore, it can form covalent bonds with four of its nearest neighbors. When temperature goes up, electrons can become free to move about the Si lattice. EE 141 4

Doping (N type) l l Si can be “doped” with other elements to change its electrical properties. For example, if Si is doped with phosphorus (P), each P atom can contribute a conduction electron, so that the Si lattice has more electrons than holes, i. e. it becomes “N type”: Notation: n = conduction electron concentration EE 141 5

Doping (P type) l If Si is doped with Boron (B), each B atom can contribute a hole, so that the Si lattice has more holes than electrons, i. e. it becomes “P type”: Notation: p = hole concentration EE 141 6

CMOS Process EE 141 7

A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process EE 141 8

Circuit Under Design EE 141 9

Its Layout View EE 141 10

The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check http: //www. fullman. com/semiconductors. html EE 141 11

Patterning of Si. O 2 Chemical or plasma etch Si-substrate Hardened resist Si. O 2 (a) Silicon base material Si-substrate Photoresist Si. O 2 (d) After development and etching of resist, chemical or plasma etch of Si. O 2 Si-substrate Hardened resist Si. O 2 (b) After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask (e) After etching Exposed resist Si. O 2 Si-substrate (f) Final result after removal of resist (c) Stepper exposure EE 141 12

Photo-Lithographic Process optical mask oxidation photoresist removal (ashing) photoresist coating stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry EE 141 13

CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers EE 141 14

CMOS Process Walk-Through p-epi (a) Base material: p+ substrate with p-epi layer p+ Si. N 34 Si. O 2 p-epi p+ (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) (c) After plasma etch of insulating trenches using the inverse of the active area mask p+ EE 141 15

CMOS Process Walk-Through Si. O 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V adjust implants Tp p (f) After p-well and V adjust implants Tn EE 141 16

CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon. Si. O 2 (i) After deposition of Si. O insulator and contact hole 2 etch. EE 141 17

CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al Si. O 2 (k) After deposition of Si. O insulator, etching of via’s, 2 deposition and patterning of second layer of Al. EE 141 18

Advanced Metallization EE 141 19

Advanced Metallization EE 141 20

Implantation l Diffusion implantation: l l l Ion implantation: l l The wafers are placed in a quartz tube embedded in a heated furnace. A gas containing the dopant is introduced in the tube. The high temperatures of the furnace, typically 900 to 1100 °C, cause the dopants to diffuse into the exposed surface both vertically and horizontally. Dopants are introduced as ions into the material. The ion implantation system directs and sweeps a beam of purified ions over the semiconductor surface. The acceleration of the ions determines how deep they will penetrate the material, while the beam current and the exposure time determine the dosage. The ion implantation method allows for an independent control of depth and dosage. EE 141 21

Deposition l Oxidation: l l l Chemical vapor deposition (CVD): l l l The wafer is exposed to a mixture of high-purity oxygen and hydrogen at approximately 1000°C. The oxide is used as an insulation layer and also forms transistor gates. CVD uses a gas-phase reaction with energy supplied by heat at around 850°C. silicon nitride (Si 3 N 4) , Polysilicon, Sputtering: l The aluminum is evaporated in a vacuum, with the heat for the evaporation delivered by electron-beam or ion-beam bombarding. EE 141 22

Etching l Wet etching: l l l It uses many types of acid, base and caustic solutions to remove a material. For instance, hydrofluoric acid buffered with ammonium fluoride is typically used to etch Si. O 2. Dry or plasma etching: l l l A wafer is placed into the etch tool's processing chamber and given a negative electrical charge. The chamber is heated to 100°C and brought to a vacuum level of 7. 5 Pa, It then filled with a positively charged plasma (usually a mix of nitrogen, chlorine and boron trichloride). The opposing electrical charges cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a microscopic chemical and physical “sandblasting” action which removes the exposed material. It creates patterns with sharp vertical contours. EE 141 23