Major CPU Design Steps 1 Using independent RTN

Major CPU Design Steps 1 Using independent RTN, write the microoperations required for all target ISA instructions. 2 Construct the datapath required by the microoperations identified in step 1. 3 Identify and define the function of all control signals needed by the datapath. 3 Control unit design, based on micro-operation timing and control signals identified: - Hard-Wired: Finite-state machine implementation. - Microprogrammed. EECC 550 - Shaaban #1 Lec # 4 Summer 2000 6 -14 -2000

Datapath Design Steps • Write the micro-operation sequences required for a number of representative instructions using independent RTN. • From the above, create an initial datapath by determining possible destinations for each data source (i. e registers, ALU). – This establishes the connectivity requirements (data paths, or connections) for datapath components. – Whenever multiple sources are connected to a single input, a multiplexer of appropriate size is added. • Find the worst-time propagation delay in the datapath to determine the datapath clock cycle. • Complete the micro-operation sequences for all remaining instructions adding connections/multiplexers as needed. EECC 550 - Shaaban #2 Lec # 4 Summer 2000 6 -14 -2000

MIPS Instruction Formats 31 R-Type I-Type: ALU 26 op 6 bits 31 26 31 J-Type: Jumps • • • rs 5 bits op 6 bits Load/Store, Branch 21 16 rt 5 bits 21 rs 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits 16 0 immediate rt 5 bits 16 bits 26 op 6 bits 0 target address 26 bits op: Opcode, operation of the instruction. rs, rt, rd: The source and destination register specifiers. shamt: Shift amount. funct: selects the variant of the operation in the “op” field. address / immediate: Address offset or immediate value. target address: Target address of the jump instruction. EECC 550 - Shaaban #3 Lec # 4 Summer 2000 6 -14 -2000

MIPS R-Type (ALU) Instruction Fields R-Type: All ALU instructions that use three registers OP 6 bits rs 5 bits rt rd shamt funct 5 bits 6 bits • op: Opcode, basic operation of the instruction. – For R-Type op = 0 • rs: The first register source operand. • rt: The second register source operand. • rd: The register destination operand. • shamt: Shift amount used in constant shift operations. • funct: Function, selects the specific variant of operation in the op field. Operand register in rs Destination register in rd Examples: add $1, $2, $3 sub $1, $2, $3 Operand register in rt and $1, $2, $3 or $1, $2, $3 EECC 550 - Shaaban #4 Lec # 4 Summer 2000 6 -14 -2000

MIPS ALU I-Type Instruction Fields I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches. • • OP rs rt 6 bits 5 bits immediate 16 bits op: Opcode, operation of the instruction. rs: The register source operand. rt: The result destination register. immediate: Constant second operand for ALU instruction. Result register in rt Examples: Source operand register in rs add immediate: addi $1, $2, 100 and immediate andi $1, $2, 10 Constant operand in immediate EECC 550 - Shaaban #5 Lec # 4 Summer 2000 6 -14 -2000

MIPS Load/Store I-Type Instruction Fields OP rs rt 6 bits 5 bits address 16 bits • op: Opcode, operation of the instruction. – For load op = 35, for store op = 43. • rs: The register containing memory base address. • rt: For loads, the destination register. For stores, the source register of value to be stored. • address: 16 -bit memory address offset in bytes added to base register in rs Offset Examples: Store word: sw 500($4), $3 Load word: lw $1, 30($2) Destination register in rt Offset source register in rt base register in rs EECC 550 - Shaaban #6 Lec # 4 Summer 2000 6 -14 -2000

MIPS Branch I-Type Instruction Fields • • OP rs rt 6 bits 5 bits address 16 bits op: Opcode, operation of the instruction. rs: The first register being compared rt: The second register being compared. address: 16 -bit memory address branch target offset in words added to PC to form branch address. Register in rt Register in rs Examples: Branch on equal beq $1, $2, 100 Branch on not equal bne $1, $2, 100 offset in bytes equal to instruction field address x 4 EECC 550 - Shaaban #7 Lec # 4 Summer 2000 6 -14 -2000

MIPS J-Type Instruction Fields J-Type: Include jump j, jump and link jal OP jump target 6 bits 26 bits • op: Opcode, operation of the instruction. – Jump j op = 2 – Jump and link jal op = 3 • jump target: jump memory address in words. Jump memory address in bytes equal to instruction field jump target x 4 Examples: Branch on equal j 10000 Branch on not equal jal 10000 EECC 550 - Shaaban #8 Lec # 4 Summer 2000 6 -14 -2000

A Subset of MIPS Instructions ADD and SUB: add. U rd, rs, rt sub. U rd, rs, rt 31 OR Immediate: ori rt, rs, imm 16 31 26 op 6 bits LOAD and STORE Word lw rt, rs, imm 16 31 26 sw rt, rs, imm 16 op 6 bits BRANCH: beq rs, rt, imm 16 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits 16 rt 5 bits 0 immediate 16 bits EECC 550 - Shaaban #9 Lec # 4 Summer 2000 6 -14 -2000

Instruction Processing Steps Instruction Fetch Next Obtain instruction from program storage Update program counter to address Instruction of next instruction Instruction Determine instruction type Decode Obtain operands from registers Execute Compute result value or status Result Store result in register/memory if needed Store (usually called Write Back). } Common steps for all instructions EECC 550 - Shaaban #10 Lec # 4 Summer 2000 6 -14 -2000

Overview of MIPS Instruction Micro-operations • • • All instructions go through these two steps: – Send program counter to instruction memory and fetch the instruction. (fetch) – Read one or two registers, using instruction fields. (decode) • Load reads one register only. Additional instruction execution actions (execution) depend on the instruction in question, but similarities exist: – All instruction classes use the ALU after reading the registers: • Memory reference instructions use it for address calculation. • Arithmetic and logic instructions (R-Type), use it for the specified operation. • Branches use it for comparison. Additional execution steps where instruction classes differ: – Memory reference instructions: Access memory for a load or store. – Arithmetic and logic instructions: Write ALU result back in register. – Branch instructions: Change next instruction address based on comparison. EECC 550 - Shaaban #11 Lec # 4 Summer 2000 6 -14 -2000

A Single Cycle Implementation Design target : A single-cycle instruction implementation All micro-operations of an instruction are to be carried out in a single system clock cycle. EECC 550 - Shaaban #12 Lec # 4 Summer 2000 6 -14 -2000

Datapath Components Instruction Word Two state elements needed to store and access instructions: 1 Instruction memory: • Only read access. • No read control signal. 2 Program counter: 32 -bit register. • Written at end of every clock cycle: No write control signal. • 32 -bit Adder: To compute the next instruction address. EECC 550 - Shaaban #13 Lec # 4 Summer 2000 6 -14 -2000

More Datapath Components Register File Main ALU Register File: • Contains all registers. • Two read ports and one write port. • Register writes by asserting write control signal • Writes are edge-triggered. • Can read and write to the same register in the same clock cycle. EECC 550 - Shaaban #14 Lec # 4 Summer 2000 6 -14 -2000

Register File Details RW RA RB Write Enable 5 5 5 • Register File consists of 32 registers: bus. A – Two 32 -bit output busses: bus. W 32 32 32 -bit bus. A and bus. B 32 Registers bus. B Clk – One 32 -bit input bus: bus. W 32 • Register is selected by: – RA (number) selects the register to put on bus. A (data): bus. A = R[RA] – RB (number) selects the register to put on bus. B (data): bus. B = R[RB] – RW (number) selects the register to be written via bus. W (data) when Write Enable is 1 Write Enable: R[RW] ¬ bus. W • Clock input (CLK) – The CLK input is a factor ONLY during write operations. – During read operation, it behaves as a combinational logic block: • RA or RB valid => bus. A or bus. B valid after “access time. ” EECC 550 - Shaaban #15 Lec # 4 Summer 2000 6 -14 -2000

Idealized Memory Write Enable Address Data In Data. Out • Memory (idealized) 32 32 – One input bus: Data In. Clk – One output bus: Data Out. • Memory word is selected by: – Address selects the word to put on Data Out bus. – Write Enable = 1: address selects the memory word to be written via the Data In bus. • Clock input (CLK): – The CLK input is a factor ONLY during write operation, – During read operation, this memory behaves as a combinational logic block: • Address valid => Data Out valid after “access time. ” EECC 550 - Shaaban #16 Lec # 4 Summer 2000 6 -14 -2000

R-Type Example: Micro-Operation Sequence For ADDU add. U rd, rs, rt OP 6 bits Instruction Word ¬ rs 5 bits Mem[PC] rt rd shamt funct 5 bits 6 bits Fetch the instruction PC ¬ PC + 4 Increment PC R[rd] ¬ R[rs] + R[rt] Add register rs to register rt result in register rd EECC 550 - Shaaban #17 Lec # 4 Summer 2000 6 -14 -2000

Building The Datapath Instruction Fetch & PC Update: Portion of the datapath used for fetching instructions and incrementing the program counter. EECC 550 - Shaaban #18 Lec # 4 Summer 2000 6 -14 -2000

Simplified Datapath For R-Type Instructions EECC 550 - Shaaban #19 Lec # 4 Summer 2000 6 -14 -2000

More Detailed Datapath For R-Type Instructions With Control Points Identified Rd Rs Reg. Wr 5 Rw 32 Clk Ra Rb 32 32 -bit Registers ALUctr 5 bus. A 32 bus. B ALU bus. W 5 Rt Result 32 32 EECC 550 - Shaaban #20 Lec # 4 Summer 2000 6 -14 -2000

R-Type Register-Register Timing Clk Old Value Rs, Rt, Rd, Op, Func PC Clk-to-Q New Value Old Value ALUctr Old Value Reg. Wr Old Value bus. A, B Old Value bus. W Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value Register File Access Time New Value ALU Delay New Value Rd Rs Rt Reg. Wr 5 5 5 bus. A 32 bus. B 32 ALU bus. W 32 Clk Rw Ra Rb 32 32 -bit Registers Register Write Occurs Here ALUctr Result 32 EECC 550 - Shaaban #21 Lec # 4 Summer 2000 6 -14 -2000

Logical Operations with Immediate Example: Micro-Operation Sequence For ORI ori rt, rs, imm 16 31 26 op 6 bits Instruction Word ¬ 21 rs 5 bits 16 rt 5 bits Mem[PC] 0 immediate 16 bits Fetch the instruction PC ¬ PC + 4 Increment PC R[rt] ¬ R[rs] OR Zero. Ext[imm 16] OR register rs with immediate field zero extended to 32 bits, result in register rt EECC 550 - Shaaban #22 Lec # 4 Summer 2000 6 -14 -2000

Datapath For Logical Instructions With Immediate Rd Reg. Dst Rt Mux Reg. Wr 5 Rw bus. W Rs 5 5 ALUctr bus. A Ra Rb 32 Clk ALU 32 32 32 -bit Registers bus. B 16 Zero. Ext imm 16 32 Mux 32 Result 32 ALUSrc EECC 550 - Shaaban #23 Lec # 4 Summer 2000 6 -14 -2000

Load Operations Example: Micro-Operation Sequence For LW lw rt, rs, imm 16 31 26 op 6 bits Instruction Word ¬ 21 rs 5 bits 16 rt 5 bits Mem[PC] 0 immediate 16 bits Fetch the instruction PC ¬ PC + 4 Increment PC R[rt] ¬ Mem[R[rs] + Sign. Ext[imm 16]] Immediate field sign extended to 32 bits and added to register rs to form memory load address, word at load address to register rt EECC 550 - Shaaban #24 Lec # 4 Summer 2000 6 -14 -2000

Additional Datapath Components For Loads & Stores Inputs for address and write (store) data Output for read (load) result 16 -bit input sign-extended into a 32 -bit value at the output EECC 550 - Shaaban #25 Lec # 4 Summer 2000 6 -14 -2000

Datapath For Loads Rd Reg. Dst Mux Reg. Wr 5 32 Clk Rs 5 5 ALUctr Rw Ra Rb 32 32 -bit Registers 32 Mem. Wr 32 ALUSrc Data In 32 Clk Mux bus. B 32 Mux 16 W_Src 32 Extender imm 16 bus. A ALU bus. W Rt Wr. En Adr Data Memory 32 Ext. Op EECC 550 - Shaaban #26 Lec # 4 Summer 2000 6 -14 -2000

Store Operations Example: Micro-Operation Sequence For SW sw rt, rs, imm 16 31 26 op 6 bits Instruction Word ¬ 21 rs 5 bits 16 rt 5 bits Mem[PC] 0 immediate 16 bits Fetch the instruction PC ¬ PC + 4 Increment PC Mem[R[rs] + Sign. Ext[imm 16]] ¬ R[rt] Immediate field sign extended to 32 bits and added to register rs to form memory store address, register rt written to memory at store address. EECC 550 - Shaaban #27 Lec # 4 Summer 2000 6 -14 -2000

Datapath For Stores Rd Reg. Dst Rt ALUctr Mem. Wr W_Src Mux Reg. Wr 5 32 Clk 5 Rt Rw Ra Rb 32 32 -bit Registers 32 Ext. Op 32 Data In 32 Clk Wr. En Adr Data Memory Mux bus. B 32 Mux 16 32 Extender imm 16 bus. A ALU bus. W 5 Rs 32 ALUSrc EECC 550 - Shaaban #28 Lec # 4 Summer 2000 6 -14 -2000

Conditional Branch Example: Micro-Operation Sequence For BEQ beq rs, rt, imm 16 31 26 21 op 6 bits Instruction Word ¬ rs 5 bits 16 rt 5 bits Mem[PC] 0 immediate 16 bits Fetch the instruction PC ¬ PC + 4 Increment PC Equal ¬ R[rs] == R[rt] Calculate the branch condition if (COND eq 0) PC ¬ PC + 4 + ( Sign. Ext(imm 16) x 4 ) else PC ¬ PC + 4 Calculate the next instruction’s PC address EECC 550 - Shaaban #29 Lec # 4 Summer 2000 6 -14 -2000

ALU to evaluate branch condition Adder to compute branch target: • Sum of incremented PC and the sign-extended lower 16 -bits on the instruction. Datapath For Branch Instructions EECC 550 - Shaaban #30 Lec # 4 Summer 2000 6 -14 -2000

More Detailed Datapath For Branch Operations Cond Instruction Address n. PC_sel 4 Adder 00 Mux bus. W PC 32 Clk Adder PC Ext imm 16 Reg. Wr 5 5 Rs 5 Rt Rw Ra Rb 32 32 -bit Registers bus. A 32 bus. B 32 Equal? 32 Clk EECC 550 - Shaaban #31 Lec # 4 Summer 2000 6 -14 -2000

Combining The Datapaths For Memory Instructions and R-Type Instructions Highlighted muliplexors and connections added to combine the datapaths of memory and R-Type instructions into one datapath EECC 550 - Shaaban #32 Lec # 4 Summer 2000 6 -14 -2000

Instruction Fetch Datapath Added to ALU R-Type and Memory Instructions Datapath EECC 550 - Shaaban #33 Lec # 4 Summer 2000 6 -14 -2000

A Simple Datapath For The MIPS Architecture Datapath of branches and a program counter multiplexor are added. Resulting datapath can execute in a single cycle the basic MIPS instruction: - load/store word - ALU operations - Branches EECC 550 - Shaaban #34 Lec # 4 Summer 2000 6 -14 -2000

Single Cycle MIPS Datapath Necessary multiplexors and control lines are identified here: EECC 550 - Shaaban #35 Lec # 4 Summer 2000 6 -14 -2000

Putting It All Together: A Single Cycle Datapath n. PC_sel 4 Rd Imm 16 Reg. Dst ALUctr Mem. Wr Equal Rd Rt 0 1 32 imm 16 16 0 1 32 Data In 32 Clk 0 32 Wr. En Adr Mux 00 Clk Extender Clk = 32 ALU bus. W Mux PC Mux Adder Rs Rt 5 5 bus. A Rw Ra Rb 32 32 -bit Registers bus. B 32 Memto. Reg. Wr 5 Adder PC Ext imm 16 Rt Instruction<31: 0> <0: 15> Rs <11: 15> Adr <16: 20> <21: 25> Inst Memory 1 Data Memory Ext. Op ALUSrc EECC 550 - Shaaban #36 Lec # 4 Summer 2000 6 -14 -2000

Adding Support For Jump: Micro-Operation Sequence For Jump: J j jump_target OP Jump_target 6 bits 26 bits Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC PC ¬ PC(31 -28), jump_target, 00 Update PC with jump address EECC 550 - Shaaban #37 Lec # 4 Summer 2000 6 -14 -2000

Datapath For Jump Next Instruction Address 32 n. PC_sel 4 JUMP Adder 00 32 PC Mux Adder imm 16 PC Ext Instruction(15 -0) 32 4 Clk PC+4(31 -28) Instruction(25 -0) jump_target 26 Shift left 2 28 32 EECC 550 - Shaaban #38 Lec # 4 Summer 2000 6 -14 -2000

<0: 25> Rd <0: 15> Rs <11: 15> Rt <16: 20> Op Fun <21: 25> Adr Instruction<31: 0> <21: 25> Instruction Memory Imm 16 Jump_target Control Unit n. PC_sel Reg. Wr Reg. Dst Ext. Op ALUSrc ALUctr Mem. Wr Memto. Reg Jump Equal DATA PATH EECC 550 - Shaaban #39 Lec # 4 Summer 2000 6 -14 -2000

Single Cycle MIPS Datapath Extended To Handle Jump with Control Unit Added EECC 550 - Shaaban #40 Lec # 4 Summer 2000 6 -14 -2000

Control Signal Generation See Appendix A func 10 0000 10 0010 Don’t Care op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add sub ori lw sw beq jump 1 1 0 0 x x x Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr<2: 0> 0 0 1 0 1 0 1 1 1 0 1 x 0 1 0 x 0 0 x Add 0 0 x Subtract 0 0 0 Or 0 0 1 Add 1 0 x 0 1 x xxx Subtract EECC 550 - Shaaban #41 Lec # 4 Summer 2000 6 -14 -2000

The Concept of Local Decoding op 00 00 1101 10 0011 10 1011 00 0100 00 0010 Reg. Dst ALUSrc Memto. Reg. Write R-type 1 0 0 1 ori 0 1 lw 0 1 1 1 sw x 1 x 0 Mem. Write Branch Jump Ext. Op ALUop<N: 0> 0 0 0 x “R-type” 0 0 Or 0 0 0 1 Add 1 0 0 1 Add op 6 Main Control func 6 ALUop jump x x x 0 0 1 0 x 0 0 1 x xxx Subtract ALUctr 3 ALU N ALU Control (Local) beq x 0 EECC 550 - Shaaban #42 Lec # 4 Summer 2000 6 -14 -2000

Local Decoding of “func” Field func op Main Control 6 ALUop (Symbolic) ALUop<2: 0> ALU Control (Local) 6 ALUop N ALUctr 3 R-type ori lw sw “R-type” 1 00 Or 0 10 Add 0 00 Instruction Operation add 10 0010 10 0101 10 1010 subtract and or set-on-less-than ALUctr ALU funct<5: 0> 10 0000 beq jump Subtract 0 01 xxx ALUctr<2: 0> 000 ALU Operation Add 001 010 Subtract And 110 111 Or Set-on-less-than EECC 550 - Shaaban #43 Lec # 4 Summer 2000 6 -14 -2000

The Truth Table for ALUctr R-type ALUop (Symbolic) “R-type” ALUop<2: 0> 1 00 ALUop bit<2> bit<1> bit<0> 0 0 x 1 0 1 x x 1 x x ori Or 0 10 lw Add 0 00 sw Add 0 00 beq Subtract 0 01 func bit<3> bit<2> bit<1> bit<0> x x x 0 0 0 1 1 0 funct<3: 0> 0000 0010 0101 1010 ALU Operation Add Subtract Or Add Subtract And Or Set on < Instruction Op. add subtract and or set-on-less-than ALUctr bit<2> bit<1> bit<0> 0 1 1 0 0 0 1 1 EECC 550 - Shaaban #44 Lec # 4 Summer 2000 6 -14 -2000

The Truth Table For The Main Control op Reg. Dst ALUSrc Memto. Reg. Write Mem. Write Branch Jump Ext. Op ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0> 00 0000 R-type 1 0 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 0 0 0 0 1 1 0 0 0 1 x 0 1 0 0 1 x 0 0 1 0 x x 0 0 0 1 x “R-type” 1 0 0 Or 0 1 0 Add 0 0 0 Subtract 0 xxx x 0 1 EECC 550 - Shaaban #45 Lec # 4 Summer 2000 6 -14 -2000

Example: Reg. Write Logic Equation op 00 00 1101 10 0011 10 1011 00 0100 00 0010 R-type 1 Reg. Write ori 1 lw 1 sw 0 beq 0 jump 0 Reg. Write = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw) . . op<5> <0> R-type . . op<5> <0> ori . . op<5> <0> lw . . op<5> <0> sw . . op<5> <0> beq op<0> jump Reg. Write EECC 550 - Shaaban #46 Lec # 4 Summer 2000 6 -14 -2000

PLA Implementation of the Main Control. . op<5> <0> R-type . . op<5> <0> ori . . op<5> <0> lw . . op<5> <0> sw . . op<5> <0> beq op<0> jump Reg. Write ALUSrc Reg. Dst Memto. Reg Mem. Write Branch Jump Ext. Op ALUop<2> ALUop<1> ALUop<0> EECC 550 - Shaaban #47 Lec # 4 Summer 2000 6 -14 -2000

Worst Case Timing (Load) Clk PC Old Value Clk-to-Q New Value Instruction Memoey Access Time New Value Rs, Rt, Rd, Op, Func Old Value ALUctr Old Value Ext. Op Old Value New Value ALUSrc Old Value New Value Memto. Reg Old Value New Value Reg. Wr Old Value New Value bus. A bus. B Delay through Control Logic New Value Register Write Occurs Register File Access Time New Value Old Value Delay through Extender & Mux Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time bus. W Old Value New EECC 550 - Shaaban #48 Lec # 4 Summer 2000 6 -14 -2000

Instruction Timing Comparison Arithmetic & Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory ALU Data Mem Store PC mux Reg File Critical Path Inst Memory Reg File ALU Data Mem Branch PC Inst Memory Reg File mux cmp mux setup mux EECC 550 - Shaaban #49 Lec # 4 Summer 2000 6 -14 -2000

Drawback of Single Cycle Processor • Long cycle time: – Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew • All instructions must take as much time as the slowest – Cycle time for load is longer than needed for all other instructions. • Real memory is not as well-behaved as idealized memory – Cannot always complete data access in one (short) cycle. EECC 550 - Shaaban #50 Lec # 4 Summer 2000 6 -14 -2000