LowPower Multipliers with Data Wordlength Reduction Kyungtae Han

Low-Power Multipliers with Data Wordlength Reduction Kyungtae Han (khan@mail. utexas. edu) Brian L. Evans (bevans@ece. utexas. edu) Earl E. Swartzlander, Jr. (eswartzla@aol. com) Dept. of Electrical and Computer Engineering The University of Texas at Austin, TX 78712 USA Asilomar Conference on Signals, Systems & Computers November 2 nd, 2005

Outline • Introduction • Wordlength reduction • Power consumption • Analysis in switching expectation • FPGA dynamic power estimation • Conclusion 2

Introduction • Minimize power dissipation due to limited battery power and cooling system • Multipliers often a major source of power consumption in typical DSP applications • Multi-precision multipliers can select smaller multipliers (8, 16 or 24 bits) to reduce power consumption • Wordlength reduction to select any word size [Han, Evans, and Swartzlander 2004] 3

Wordlength Reduction in Multiplication Sign bit • Input data wordlength reduction – Smaller bits enough to represent, e. g. π x π ≈ 9 • Truncation • Signed right shift – Move toward the least significant bit (LSB) – Signed bit extended for arithmetic right shift 4

Power Reduction via Wordlength Reduction • Power dissipation – Switching power consumption – Static power consumption • Switching power consumption – Switching activity parameter, α – Reduce α by wordlength reduction CL Load capacitance Vdd Operating voltage fclk Operating frequency What is relationship between wordlength and switching parameter, α, in power consumption? 5

Switching Activity in Multipliers • Logic delay and propagation cause glitches • Proposed analytical method – Hard to estimate glitches in closed form – Analyze switching activity w/r to input data wordlength – Does not consider multiplier architecture • Simulation method – Count all switching activities (transition counts in logic) – Power estimation (Xilinx XPower) – Considers multiplier architecture 6

Analytical Method • Consider stream of data for one of the multiplicands • Compare two adjacent numbers in stream after reduction L bits • Expectation of bit M bits N bits switching, x, with probability Px … … S – L-bit input data – Truncate input data to M bits (N bits are removed) – N-bit signed right shift in L-bit input (Y is sign bit) S … S S … 7

Analytical Method X has binomial distribution Always L/2 (independent on M and N) 8

Analytical Method Input Switching expectation Full length used L/2 Truncate N bits M/2 N-bit signed right shift L/2 Wordlength (L) = 16 9

Wallace vs. Booth Multipliers Symmetric Asymmetric (one operand recoded) Tree dot diagram in 4 -bit Wallace multiplier Radix-4 multiplier based on Booth’s recoding (Χ ● a = P) 10

Dynamic Power Consumption for Wallace Multiplier (1 MHz) Reduction (56%) 16 -bit x 16 -bit multiplier (Simulated on XC 3 S 2005 FT 256 FPGA) Swapping (recode, nonrecode) 11

Dynamic Power Consumption for Radix-4 Modified Booth Multiplier (1 MHz) Sensitive (13%) 16 -bit x 16 -bit multiplier (Simulated on XC 3 S 2005 FT 256 FPGA) Reduction (31%) Swapping (recode, nonrecode) 12

Conclusion • Truncation to 8 bits reduces est. power consumption by 56% in Wallace and 31% in Booth 16 -bit multipliers • Signed right shift exhibits no est. power reduction in Wallace multiplier (for any shift) and 25% reduction in Booth multipliers (for 8 -bit shift) • Power consumption in tree-based multiplier – Highly depends on input data – Simulation of all switching activity matches analysis of switching activity in reduced multiplicands in Wallace mult. • Operand swapping can reduce power consumption – In Booth multiplier, non-recoded operand 13% more sensitive in power consumption 13

Thank You! 14

Backup Slides 15

Dynamic Power Consumption • 16 -bit x 16 -bit multiplier (Simulated on XC 3 S 2005 FT 256 FPGA) 31% 56% Swapping Wallace multiplier (1 MHz) Radix-4 modified Booth multiplier (1 MHz) 16