LowPower Design of Digital VLSI Circuits Introduction to

Low-Power Design of Digital VLSI Circuits Introduction to Low Power Design Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng. auburn. edu http: //www. eng. auburn. edu/~vagrawal Copyright Agrawal, 2011 Lecture 1: Introduction 1

Course Objectives Low-power is a current need in VLSI design. l Learn basic ideas, concepts, theory and methods. l Gain experience with techniques and tools. l Copyright Agrawal, 2011 Lecture 1: Introduction 2

Course Description This course is designed for the MTech program in VLSI at IIT, Delhi. It is patterned after a one-semester graduate-level course offered at Auburn University. A set of 16 lectures that include classroom exercises provide understanding of theoretical and practical aspects of power and energy in digital VLSI systems. The course fulfills a basic need of today’s industrial design environment. Specific topics include power components of digital CMOS circuits, power analysis, glitch elimination for reducing dynamic power, dual-threshold design for reduced static power, voltage and frequency scaling*, power management in memories* and microprocessors*, parallelism for power saving, battery management*, test power*, and ultra-low voltage (subthreshold) logic circuits*, low power technologies (domino CMOS, pass transistor logic)*, adiabatic logic*. ________ * Not included in short course. Copyright Agrawal, 2011 Lecture 1: Introduction 3

l l l l l l Outline Lecture 1: Introduction (37) * Number of slides Homework 1 (10 points) Lecture 2: Power dissipation of CMOS Circuits (46): Lecture 3: Power of a transition Lecture 4: Dynamic (logic, glitch, short-circuit) power, static power Homework 2 (10 points) Lecture 5: Gate-level power analysis (56): Lecture 6: Logic simulation, delay estimation Lecture 7: Transition density, Probabilistic methods Lecture 8: Power calculation Homework 3 (10 points) Lecture 9: Linear Programming – A Mathematical optimization technique (44): Lecture 10: Examples of LP and ILP optimization Homework 4 (10 points) Lecture 11: Gale-level power optimization (59): Lecture 12: Glitch-free design for reduced dynamic power Lecture 13: Dual-threshold design for reduced leakage Lecture 14: Examples Lecture 15: Multicore design for low power (23) Homework 5 (10 points) Lecture 16: Test Power (52) Lecture 17: Test Power (continued) EXAM (50 points) Copyright Agrawal, 2011 Lecture 1: Introduction 4

Schedule l l l July 26, 2011 – 4: 00 -5: 30 PM Lecture 1 July 27, 2011 – 4: 00 -5: 30 PM Lectures 2 and 3 July 28, 2011 – 4: 00 -5: 30 PM Lectures 4, 5 and 6 July 29, 2011 – 4: 00 -5: 30 PM Lectures 6 (cont. ), 7 and 8 July 30, 2011 – 4: 00 -5: 30 PM Lectures 9 and 10 Aug 1, 2011 – 4: 00 -5: 30 PM Lectures 11 and 12 Aug 2, 2011 – 4: 00 -5: 30 PM Lectures 13 and 14 Aug 3, 2011 – 4: 00 -5: 30 PM Lecture 15 Aug 4, 2011 – 4: 00 -5: 30 PM Lecture 16 Aug 5, 2011 – 4: 00 -5: 30 PM Lecture 17 Aug 6, 2011 – EXAM Copyright Agrawal, 2011 Lecture 1: Introduction 5

Power Consumption of VLSI Chips Why is it a concern? Copyright Agrawal, 2011 Lecture 1: Introduction 6

ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10 GHz to 30 GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP. Copyright Agrawal, 2011 “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . ” Lecture 1: Introduction 7

VLSI Chip Power Density Sun’s Surface Power Density (W/cm 2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 Hot Plate 10 4004 8008 8085 386 286 8080 1 1970 Copyright Agrawal, 2011 1980 P 6 Pentium® 486 1990 Year Lecture 1: Introduction Source: Intel 2000 2010 8

SIA Roadmap for Processors (1999) Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic transistors/cm 2 6. 2 M 18 M 39 M 84 M 180 M 390 M Clock (GHz) 1. 25 2. 1 3. 5 6. 0 10. 0 16. 9 Chip size (mm 2) 340 430 520 620 750 900 Power supply (V) 1. 8 1. 5 1. 2 0. 9 0. 6 0. 5 High-perf. Power (W) 90 130 160 175 183 Source: http: //www. semichips. org Copyright Agrawal, 2011 Lecture 1: Introduction 9

Recent Data Source: http: //www. eetimes. com/story/OEG 20040123 S 0041 Copyright Agrawal, 2011 Lecture 1: Introduction 10

Low-Power Design l Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable. l Low-power design methods: l Algorithms and architectures l High-level and software techniques l Gate and circuit-level methods l Test power Copyright Agrawal, 2011 Lecture 1: Introduction 11

VLSI Building Blocks Finite-state machine (FSM) l Bus l Flip-flops and shift registers l Memories l Datapath l Processors l Analog circuits l RF components l Copyright Agrawal, 2011 Lecture 1: Introduction 12

Specific Topics in Low-Power l l Power dissipation in CMOS circuits Device technology l l l Circuit and gate level methods l l l l Logic synthesis Dynamic power reduction techniques Leakage power reduction System level methods l l Low-power CMOS technologies Energy recovery methods Microprocessors Arithmetic circuits Low power memory technology Test Power estimation Copyright Agrawal, 2011 Lecture 1: Introduction 13

Some Examples Copyright Agrawal, 2011 Lecture 1: Introduction 14

State Encoding for a Counter l Two-bit binary counter: l State sequence, 00 → 01 → 10 → 11 → 00 l Six bit transitions in four clock cycles l 6/4 = 1. 5 transitions per clock l Two-bit Gray-code counter l State sequence, 00 → 01 → 10 → 00 l Four bit transitions in four clock cycles l 4/4 = 1. 0 transition per clock l Gray-code counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998. Copyright Agrawal, 2011 Lecture 1: Introduction 15

Binary Counter: Original Encoding Present state a Next state b a 0 b 0 A 0 B 1 0 1 1 1 0 0 1 0 A = a’b + ab’ = a xor b B = a’b’ + ab’ = b’ Copyright Agrawal, 2011 A B CK CLR Lecture 1: Introduction 16

Binary Counter: Gray Encoding Present state Next state a 0 b 0 A 0 B 1 0 1 1 0 0 A = a’b + ab = b B = a’b’ + a’b = a’ Copyright Agrawal, 2011 a A B b CK CLR Lecture 1: Introduction 17

Three-Bit Counters State Binary No. of toggles Gray-code State No. of toggles 000 - 001 1 010 2 011 1 010 1 100 3 110 1 101 1 110 2 101 1 111 1 100 1 000 3 000 1 Av. Transitions/clock = 1. 75 Copyright Agrawal, 2011 Lecture 1: Introduction Av. Transitions/clock = 1 18

N-Bit Counter: Toggles in Counting Cycle l l l Binary counter: T(binary) = 2(2 N – 1) Gray-code counter: T(gray) = 2 N T(gray)/T(binary) = 2 N-1/(2 N – 1) → 0. 5 Bits T(binary) T(gray)/T(binary) 1 2 2 1. 0 2 6 4 0. 6667 3 14 8 0. 5714 4 30 16 0. 5333 5 62 32 0. 5161 6 126 64 0. 5079 ∞ - - 0. 5000 Copyright Agrawal, 2011 Lecture 1: Introduction 19

FSM State Encoding Transition probability based on PI statistics 0. 6 11 0. 3 0. 4 00 0. 6 0. 1 0. 3 0. 1 01 01 0. 4 0. 9 00 0. 6 0. 1 11 0. 9 Expected number of state-bit transitions: 2(0. 3+0. 4) + 1(0. 1+0. 1) = 1. 6 1(0. 3+0. 4+0. 1) + 2(0. 1) = 1. 0 State encoding can be selected using a power-based cost function. Copyright Agrawal, 2011 Lecture 1: Introduction 20

FSM: Clock-Gating l Moore machine: Outputs depend only on the state variables. l If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. Xi/Zk Si Sk Sj Copyright Agrawal, 2011 Xk/Zk Clock can be stopped when (Xk, Sk) combination occurs. Xj/Zk Lecture 1: Introduction 21

Clock-Gating in Moore FSM PI Flip-flops Combinational logic Clock activation logic CK Copyright Agrawal, 2011 Latch PO L. Benini and G. De Micheli, Dynamic Power Management, Boston: Springer, 1998. Lecture 1: Introduction 22

Bus Encoding for Reduced Power l Example: Four bit bus l 0000 → 1110 has three transitions. l If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. Bit-inversion encoding for N-bit bus: Number of bit transitions after inversion encoding l Copyright Agrawal, 2011 N N/2 0 0 N/2 Number of bit transitions Lecture 1: Introduction N 23

Sent data Received data Bus-Inversion Encoding Logic Polarity decision logic Copyright Agrawal, 2011 Bus register Polarity bit M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O, ” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 49 -58, March 1995. Lecture 1: Introduction 24

Clock-Gating in Low-Power Flip-Flop D D Q CK Copyright Agrawal, 2011 Lecture 1: Introduction 25

Example: Benchmark S 5378 l l TSMC 025 CMOS technology 50 ns clock 1, 000 random vectors Reference: J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s Thesis, Auburn University, December 2008, Section 3. 8. Clock Number of comb. of flipgates flops Power consumption in μW Comb. gates Flip-flops Total Ungated 2, 958 179 330 752 1, 082 Gated 3, 316 179 276 32 308 Copyright Agrawal, 2011 Lecture 1: Introduction 26

Example: Shift Register D D Q D Q Output D Q D Q CK Copyright Agrawal, 2011 Lecture 1: Introduction 27

Reduced-Power Shift Register D Q D Q multiplexer D D Q D Q D Output Q CK(f/2) Flip-flops are operated at full voltage and half the clock frequency. Copyright Agrawal, 2011 Lecture 1: Introduction 28

Power Consumption of Shift Register 16 -bit shift register, 2μ CMOS Freq (MHz) Power (μW) 1 33. 0 1535 2 16. 5 887 4 8. 25 738 C. Piguet, “Circuit and Logic Level Design, ” pages 103 -133 in W. Nebel and J. Mermet (ed. ), Low Power Design in Deep Submicron Electronics, Springer, 1997. Normalized power 1. 0 Deg. of parallelism Copyright Agrawal, 2011 P = C’VDD 2 f/n 0. 5 0. 25 0. 0 Lecture 1: Introduction 1 2 4 Degree of parallelism, n 29

Books on Low-Power Design (1) l l l l L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. J. -M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC & Custom: Tools and Techniques for Low Power Design, Springer, 2007, ISBN 0387257632, 9780387257631. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low. Power Digital Circuit Techniques, Boston: Springer, 1997. Copyright Agrawal, 2011 Lecture 1: Introduction 30

Books on Low-Power Design (2) l l l l P. Girard, N. Nicolici and X. Wen, Power-Aware Testing and Test Strategies for Low Power Devices, Springer, 2010. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. M. Keating, D. Flynn, R. Aitken, A. Gibbons and K. Shi, Low Power Methodology Manual For System-on-Chip Design, 1 st ed. 2007. Corr. 2 nd printing, 2007, XVI, 304 p. , Hardcover, ISBN: 978 -0 -38771818 -7. J. B. Kuo and J. -H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley-Interscience, 1999. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. Copyright Agrawal, 2011 Lecture 1: Introduction 31

Books on Low-Power Design (3) l l l l W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997. N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. Copyright Agrawal, 2011 Lecture 1: Introduction 32

Books on Low-Power Design (4) l l l K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley-Interscience, 2000. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston: Springer, 1995. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: Springer, 2001. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Springer, 1998. K. -S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, Mc. Graw Hill, 2004. Copyright Agrawal, 2011 Lecture 1: Introduction 33

Books Useful in Low-Power Design l l l l A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High. Performance Microprocessor Circuits, New York: IEEE Press, 2001. R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, Mc. Graw-Hill, 2006. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: Mc. Graw-Hill, 1996. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice. Hall, 2003. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005. Copyright Agrawal, 2011 Lecture 1: Introduction 34

Problem: Bus Encoding A 1 -hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1 -hot encoding to be beneficial. Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224 -225. [Hint: You should be able to solve this problem without the help of the reference. ] Copyright Agrawal, 2011 Lecture 1: Introduction 35

Solution: Bus Encoding Un-coded bus: Two consecutive bits on a wire can be 00, 01, 10 and 11, each occurring with a probability 0. 25. Considering only the 0→ 1 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2 n/4. Encoded bus: Encoded bus contains 2 n wires. The 1 -hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2 n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2–n, and CV 2 with probability 1 – 2–n. The average per pattern energy for the 1 -hot encoded bus is CV 2(1 – 2–n). Copyright Agrawal, 2011 Lecture 1: Introduction 36

Solution: Bus Encoding (Cont. ) Power ratio = Encoded bus power / un-coded bus power = 4(1 – 2–n)/n → 4/n for large n For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2–n)/n ≤ 1, or 1 – 2–n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4. The following table shows 1 -hot encoded bus power ratio as a function of bus width: n 4(1 – 2–n)/n 1 2. 0000 8 0. 4981 2 1. 5000 16 0. 2500 = 1/4 3 1. 1670 32 1/8 4 0. 9375 64 1/16 Copyright Agrawal, 2011 Lecture 1: Introduction 37