Low Voltage Scalable Nanocrystal FLASH Memory Fabricated by

Low Voltage, Scalable Nanocrystal FLASH Memory Fabricated by Templated Self Assembly Sung Hyun Jo Ph. D. Student, Dept. of Electrical Engineering & Computer Science Ken Loh Ph. D. Student, Dept. of Civil & Environmental Engineering EECS 598 Nanoelectronics October 11, 2005

Research Motivation q Nanocrystal FLASH memory offers potential advantages over traditional FLASH devices. v v v q Introduce new method for building nanocrystal FLASH memory devices that achieves precise control of nanocrystal size and position. v q Improved scalability Retention Cyclability Dimensions are defined via polymer self assembly Device exhibit low voltage memory operation with promising retention and endurance properties. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Background on Conventional FLASH q What is FLASH memory? v v Form of non-volatile EEPROM that allows multiple memory locations to be erased or written within one programming cycle Unlike EEPROM that only allows one location to be erased/written at one time Table: Conventional FLASH Memory Pros: q Cons: q Non-volatile q 10, 000 erase operation lifetime q Fast read/access time q Size limitation q Shock resistant q High power consumption Significant problem of limited, short lifetime for read and access v Erase operation causes wear and tear of insulating oxide layer around the charge storage mechanism Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Two Main Types of Conventional FLASH q NOR Flash v v v q Each cell looks like a MOSFET transistor, except having two gates instead of one v One gate is the control gate (CG) like in other MOS transistors v Second gate is the floating gate (FG) that is insulated by the oxide layer Because the FG is insulated in an oxide layer, any electrons placed on it gets trapped and retains information Programming the NOR flash involves starting the flow of electrons from source to drain and then applying a large enough electric field to suck them up to the FG through quantum tunneling NAND Flash v Programming methodology is different v Tunnel injection to write v Tunnel release to erase Right: i. Pod Nano using two 2 -Gb Samsung FLASH chips Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Background (1) q The trend of nonvolatile memories v v v q Storage capability enhancement High speed Low power Scale down Problems of conventional Flash memory scaling down v v v Tunneling oxide v Very sensitive to defects v Cycling induced defects High operation voltage (~10 V) The length scaling Control Gate e- e. Defect Source Channel Flash Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 Continuous FG Drain

Background (2) q Solution for scaling down of nonvolatile memory devices v v High quality tunneling oxide High-K material New nonvolatile memory technologies v Fe. RAM, MRAM, PCRAM … Discrete-trap memory devices v Relatively insensitive to oxide defects Control Gate Distributed Nodes e- Control Gate e- Nanocrystals e- e- e. Source Control Gate Defect Channel Drain Discrete-Trap Memory Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 Source e- e- e- Drain Source e- e- e- Channel SONOS NFGM Drain

Background (3) q q The Advantages of Discrete-Trap Memory v Scaling down of tunneling oxide (<<8 nm) v Low W/E voltage & low power v Fast write time v High endurance/reliability (reduced hot carrier effect) v Long retention time (relatively insensitive to defects) Issues v Retention time versus Write time optimization v Large window of threshold voltage (∆VTH) Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Discrete-Trap Memory Device q Case 1 : Tiwari’s structure v The first proposed nanocrystal based memory device. Dot density: ~1011/cm 2 Control oxide Source Compared to flash EEPROM Tunnel oxide Nanocrystals Drain o Fast read time o Long retention time o Low power Tiwari, IEDM Tech. Dig 521 1995 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Discrete-Trap Memory Device q Case 2 : Guo’s structure Control gate Dot Oxide Si channel Buried oxide Si substrate o Noble E-beam lithography o SOI technology o Unfavorable for mass production at present L. J. Guo, Science, vol. 275, pp. 649 -651, 1997. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

q Case 3 v v The film growth Photo-CVD v Low growth rate v No plasma damage Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Formation of Si Nanocyrtal q Si Nanocrystal The TEM image 5 nm Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Formation of Si Nanocyrtal q The Variable: Deposition Time t : 2 min Size Density t : 3 min t : 5 min Increased deposition time Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Formation of Si Nanocyrtal q The Variable: Hydrogen dilution ratio (R = H 2/Si. H 4) R = 15 Size Density R = 20 R = 25 R Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

A breakthrough improvement of the nanocrystal memory is expected with a material that incorporates ordered Si nano-dots of equal sizes and equal distances between them!!! Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Introduction q What Nanocrystal FLASH memory has to offer v v q In addition to the previously mentioned advantages… The floating gate is composed of discrete, electrically-isolated particles v Compared to a continuous film in conventional FLASH v Typically formed by CVD or aerosol deposition v Such nanocrystals have a wide distribution of size and position, leading to limitations on device performance, scalability, and manufacturability Solution: New fabrication method for building nanocrystal memories v Based on a polymer self assembly process v Sets nanocrystal dimensions, density, and uniformity Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Fabrication q Define Si nanocrystals using diblock copolymer thin film selfassembly v v v Involves spin coating a dilute polymer solution Diblock copolymer consists of: v Polystyrene (PS) v Poly(methyl methacrylate) (PMMA) v Molecular weight ratio produces hexagonally-close packed PMMA cylinders in a PS matrix Annealing to promote phase separation into nanometer-scale polymer domains PMMA is removed with an organic solvent, leaving a porous PS film Thin film used as sacrificial layer to define nanocrystals at sub-lithographic dimensions Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

The Diblock Copolymer q Diblock copolymer composed of polystyrene (PS) and poly(methyl methacrylate) (PMMA) – What are they? v v v q Diblock copolymer are composed of two chemically distinct polymers When films of diblock copolymer are annealed, nanometer-scale patterns form due to phase separation v Separations called “microdomains” can be observed The stripe pattern is formed from repulsion between the two halves of the polymer molecules PS / PMMA v The MW ratio produces hexagonally-close packed PMMA cylinders in a PS matrix Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

The Polymers q PMMA – Poly(Methyl Methacrylate) v q Form acrylic plastics used in many common products PS – Polystyrene v A liquid hydrocarbon that is commercially manufactured from petroleum Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

An Example of structures produced by block copolymer nanolithography Left: SEM image of an array of holes (aspect ratio near unity) in a Si wafer. Right: TM-AFM image of an array of metallic Au dots fabricated in a trilayer process. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Outline of Fabrication Steps 1) Form the porous PS film on a thermal oxide hardmask. 2) Etch PS pattern into oxide 3) Grow program oxide (2 -3 nm) and conformally deposit a: Si 4) Etch a: Si using an anisotropic reactive ion etching (RIE) process Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Fabrication Process I q Top Figure v v v q 200 x 200 nm SEM image of porous polymer film on silicon oxide Indicates polymer molecules are made to self -assemble in hexagonal arrangements Size of arrangement set by size of polymer molecules Bottom Figure v v Porous polymer film on silicon oxide (after etching of PMMA) Benefits: v This polymer is more rugged to withstand higher temperatures during fabrication v Polymer material can be easily removed Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Fabrication Process II q Top Figure v v v q Si nanocrystal array Combination of depositing silicon material and etching leaves Si nanocrystals Embedded within 20 nm region defined by self assembled polymer matrix Bottom Figure v v v Dotted curve (a): dimensions of hexagonal pattern of initial polymer layer maintained throughout Gray curve (b): dimensions of hexagonal pattern during intermediate process Solid curve (c): final silicon nanocrystal dimensions Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Resulting a: Si Nanocrystals q A: Si nanocrystals reproduce dimension of the original selfassembled polymer film v v v Diameter: 20 nm ± 10% Center-to-center spacing: 40 nm (hexagonal close-packed) Nanocrystal density: 6. 5 x 1010/cm 2 Left: Example of nanocrystal formation on substrate. q Smaller nanocrystals can be formed by employing lower molecular weight polymers v Potential source for future device scaling Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

How it Works q Devices are programmed by injecting charge erased by expelling charge from the nanocrystals v v Process of quantum tunneling as before Simply speaking, if the potential of the electrons are high enough, the electron particles can tunnel through the potential energy barrier instead of being insulated by the oxide Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Experimental Results Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q The stored charge shifts the device flat band voltage, VFB Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q q A write voltage, VW, of -4 V shifts VFB by > 0. 5 V. Larger VFB shifts are achieved with higher VW. Magnitude and slope of ΔVFB vs. VW depend on the program and control oxide thicknesses Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q ΔVFB saturates at high VW, when charge begins to leak through the control oxide Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q Devices with tprog = 3 nm show larger ΔVFB than tprog = 2 nm at long write times due to larger voltage on the floating gate for the same V W Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q ΔVFB increases with write time for a fixed VW q Minimum write time of 50 micro-s provides ~0. 2 VFB at VW = -6 V v q Device A Fully erase the devices with a 100 micro-s erase voltage (VE) pulse of +4 V Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q Evaluate stability of the written and erase memory v v Using VW = -6 V, VE = +4 V Measure signal capacitance at -2 V as a function of time Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Device Performance q Measuring device endurance v For tctrl = 2 nm Measured using VW = -6 V, 50 micro-s, and VE = +4 V, 50 micro-s Capacitance in the two memory states was read at -2 V v Device write/erase window remains unchanged out to 109 cycles v v Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Discussion q q q Describe first nanocrystal FLASH that utilizes self-assembled polymer film to build Si nanocrystals This is a manufacturable solution to achieve uniformly-sized and – spaced nanocrystals Device functions as a nonvolatile memory element v ΔVFB > 0. 5 V for VW < 4 V q Retention time > 106 s for program oxide as thin as 2 nm q Endurance > 109 cycles Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Status and Outlook of Emerging Nonvolatile Memory Technologies Ken Loh Ph. D. Student, Dept. of Civil & Environmental Engineering Sung Hyun Jo Ph. D. Student, Dept. of Electrical Engineering & Computer Science EECS 598 Intro. To Nanoelectronics Oct 11, 2005

Emerging Nonvolatile Memory Technologies q Category v Reversible Conductance Change v Conductive Bridging RAM (CBRAM) v The state change (amorphous, crystalline) v v v The Magneto-resistive RAM (MRAM) v The magneto resistance Phase Change RAM (PCRAM) v The state change (amorphous, crystalline) Other v Ferro-electric RAM (Fe. RAM) v The Residual polarization in ferroelectrics Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Conductive Bridging RAM (CBRAM) q q q Based on a polarity-dependent resistive switching Metal/a-Si: H/Metal structure Electroforming process v v Sufficient applied voltage causes atoms from the top contact to enter the a. Si: H, and leave metallic inclusions (*still controversial) The forming process operate by diffusion Top Metal a-si: H Bottom Metal M. Jafar Phy. Rev. B vol. 49, 1994 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

CBRAM q Voltage-current characteristic M. Jafar Phy. Rev. B vol. 49, 1994 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

CBRAM q Performance improvement by replacing a-Si: H as chalcogenide glass (Ge 2 Sb 2 Te 5, GST) v v v Small device size (~100 nm) High Roff/Ron ratio Retention time Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Ferro-electric RAM (Fe. RAM) q Fe. RAM stores data as remnant polarization in a ferroelectric capacitor The hysteresis in ferroelectrics Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Fe. RAM q Capacitor Type RAM v v Destructive Read Small size is the most challenging issue Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Fe. RAM - Scaling down q Conventional Problem To obtain certain amount of polarization, the size of the capacitor is limited (as for the planar Fe. RAM, size of the capacitor is ~10 F 2) v q The capacitor on plug structure (~4 F 2) v High aspect ratio required Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Magneto-resistive RAM (MRAM) q MRAM uses magnetic moments, rather than an electric charge, to determine the on-off state of the memory bit cell. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

MRAM q TMR (Tunneling Magneto Resistance) Current The ferromagnetic layer (Fe, Ni, Co) The insulator layer (Al 2 O 3 –pin hole free ) The direction of magnetic field (a) Small Resistance An electron with a given spin direction can only tunnel into an empty state with the same spin direction Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 (b) Large Resistance

MRAM q Magneto Tunnel Current S. Tehrani, Proceeding of IEEE, 91, 2003, p. 703 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

MRAM q Read & Write principle Write Pulse Sensing Voltage TMR selection (off) Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 TMR (on)

MRAM The free layer of the bit is elongated in shape : Magnetic shape anisotropy creates an energy barrier S. Tehrani, Proceeding of IEEE, 91, 2003, p. 703 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

MRAM q Scaling Issue v v To maintain or increase the readout speed even if the bit size is reduced, it is essential that the MTJ resistance dose not increase v Decrease of barrier thickness & the barrier height (lower resistance-area) Ferromagnetic material v Today’s alloys can produce MR of 50% v Replacing one electrode with a material having polarization over 90% would increase MR to 150% Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Phase Change RAM (PCRAM) q Based on a thermally induced reversible phase change between the amorphous (high R) and the crystalline (small R) phase of a chalcogenide (Ge 2 Sb 2 Te 5, GST) v High current & fast quenching freezes the material to amorphous state (10~30 ns). Medium current for longer pulse time is used for re-crystallization The Conceptual PRAM Vcc GST Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

PCRAM q I-V curves for the crystalline and amorphous chalcogenide * A. Pirovano, IEEE Trans. On Elec. Dev. 51 p. 452 2004 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 * G. Muller, IEEE

PCRAM q Reliability v Over heating of a cell degrades the endurance *S. Lai, IEDM Tech. Dig. , 2003, p. 256 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

PCRAM q q Issues Switching current reduction: power consumption, switching time v Reducing the contact area is essential *S. Lai, IEDM Tech. Dig. , 2003, p. 256 Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Comparison Flash CBRAM Fe. RAM MRAM PCRAM Maturity Product Single Cells Product Samples Product Sample Density 4 Gb - 32 Mb 16 Mb 64 Mb Cell Size[um 2] 0. 025 - 0. 6 1. 4 0. 5 Nonvolatile Yes Yes Yes Random Read Access 80 ns <200 ns 50 ns 30 ns 50 ns Random Write Access ~10 us (erase 100 ms) <200 ns 70 ns 30 ns 50 ns Destructive Read No No Yes No No Write Endurance 106 >105 >1012 1015 >1012 Write Voltage Vdd+~10 V Vdd Vdd Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Conclusions q Fabrication of Si nanocrystals feasible using diblock copolymer v v q Smaller nanocrystals can be fabricated using a similar fashion by employing different diblock copolymers v q PS-PMMA diblock copolymer Self-assembly technique Scalable Memory retention and endurance verified through experiments Potential technique for future scalable operations Potential candidates for emerging nonvolatile memory storage devices v v CBRAM MRAM PCRAM Fe. RAM Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Programming & Erasing Mechanism of the Floating gate memory device Ken Loh Sung Hyun Jo EECS 598 Intro. To Nanoelectronics Oct 11, 2005

Basic Programming Mechanism q Fowler-Nordheim (FN) tunneling v v q Uniform tunneling Drain side tunneling Hot carrier injection v v v Hot electrons (CHE) Hot holes (CHH) Modeling method v e. g. Lucky-electron model (by Shockley) Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Fowler-Nordheim (FN) tunneling q N-type on p-sub Energy band diagram of a floating gate memory during programming by FN tunneling. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

q FN tunneling (during the programming) Uniform tunneling Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 Drain side tunneling

Hot carrier injection (HCI) q Hot electron injection v Hot-hole injection is slow due to large mass and energy barrier of 4. 7 e. V Hot-electron injection mechanism for programming in NVM's. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Hot Carrier Injection Modeling q Lucky-electron Model (by Shockley) v v v Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005 A-B: The hot electron momentum has to be redirected towards the interface. (with probability PA ) B-C: The hot electron must not suffer any energy robbing collision (PB) C-D: The electron must not suffer any scattering due to the oxide image potential (PC)

Basic Erasing Mechanism q q The net negative charge confined in the floating gate shifts the V T to a positive value Two methods of erasing v v UV emission (EPROM) FN tunneling v Uniform tunneling v Drain side tunneling Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

UV Emission q The typical time it takes to change the VT from programmed state to neutral or erased state is 10 minutes (EPROM) Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

FN tunneling q N-type on p-sub Energy band diagram of a floating gate memory during erasing by FN tunneling. Nonvolatile Memories EECS 598 Nanoelectronics – Tuesday, Oct 11, 2005