Low Power RF Low Noise Amplifier Rakshith Venkatesh

Low Power RF Low Noise Amplifier Rakshith Venkatesh 4/27/2009 1

What is an RF Low Noise Amplifier? �The low-noise amplifier (LNA) is a special type of amplifier used in the receiver side of communication systems to amplify very weak signals captured by an antenna. �RF means high frequency (hundreds of MHz to GHz). �The job of the LNA is to boost the incoming signal power while adding as little noise and distortion as possible to this received signal. �For example, the 5 GHz frequency band is the used for wireless communication. IEEE 802. 11 wireless standard uses this frequency band. 4/27/2009 2

About this project: The main intension is to design a low power RF amplifier without sacrificing the amplifier gain and its Noise-Figure (SNR_in/SNR_out). 4/27/2009 Typical values of conventional design and my objective Cascode Design Low Power Design Technology 90 nm Frequency 5. 5 GHz Gain >13 d. B > 12 d. B Power Dissipation >8 m. W < 4 m. W Noise Figure ~2 -3 d. B < 4 d. B S 12 <-25 d. B < -25 d. B 3

Design Steps � The bias current (0. 13 m. A/um) is selected and then the ‘W’ of the transistors based on this. The supply voltage is decided based on the number of stages stacked and the gain needed. Start off with the ‘Vdd’ specified for the technology. � The MOSETs are biased and we must ensure that all the transistors are operating in the saturation region (Vds > Vgs – Vth). Gate biasing voltage is calculated using the transfer characteristics of the stage. � Impedance matching at the input stage of the amplifier is done so that the input impedance is equal to 50 Ohm, the series resistance of the RF signal source. � Output impedance matching is done assuming the device is terminated at 50 Ohm. In other words the load resistance is 50. � The simulation is run using ‘HSPICE’ and the parameters like S 21(gain), S 11, S 22, S 12, NFmin and power dissipation are calculated. 4/27/2009 4

Conventional Design of an LNA Ref: ‘ 60 -GHz PA and LNA in 90 -nm RF-CMOS’, Yao T et. al, Radio Frequency Integrated Circuits Symposium, 2006, IEEE, 4 pp. 4/27/2009 5

Circuit Diagram of the LNA in this work 4/27/2009 6

S 21 or Gain of the designed LNA 4/27/2009 7

S 12 or Reverse Isolation 4/27/2009 8

S 11 plot 4/27/2009 9

S 22 plot 4/27/2009 10

NF with Nfmin = 3. 5 d. B 4/27/2009 11

Power Calculation The bias current of the circuit is 3. 2 m. A and the power supply voltage is 1. 5 V. Hence, Power Dissipation = Bias Current. Vdd = 4. 8 m. W 4/27/2009 12

Comparison with low power designs Parameter Paper[1] Paper[2] This work 250 90 90 2 1. 5 Frequency (GHz) 2. 4 5. 5 5. 0 Gain (d. B) 14. 7 15. 4 13 Noise Figure(d. B) 2. 5 2. 7 5. 6 Power (m. W) 1. 97 20. 6 4. 8 S 12 (d. B) -28 -32 -45. 86 S 11 (d. B) -20 -14 -10. 3 S 22 (d. B) -22 -8. 8 -14. 5 Technology (nm) Voltage Supply (V) [1] ‘Design of a New Low-Power 2. 4 GHz CMOS LNA’, Ickjin Kwon and Hyungcheol Shin Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 47 [2] ‘Low-power 5 GHz LNA and VCO in 90 nm RF CMOS’ , D. Linten et. al, VLSI Circuits 2004, Digest of Technical Papers. 2004 Symposium, 17 -19 June 2004, 372 - 375. 4/27/2009 13

Comparison with normal designs Parameter Paper[3] Paper[4] This Work Technology(nm) 90 90 90 Voltage Supply (V) 1. 2 1. 5 Frequency (GHz) 5. 5 3. 1 to 5. 9 5. 0 Gain (d. B) 13. 3 13. 5 13 NF (d. B) 2. 9 2. 8 – 3. 8 5. 6 Power (m. W) 9. 72 5. 4 4. 8 S 12 (d. B) -28 <-57 -45. 86 S 11 (d. B) -14. 4 ~ - 15 -10. 3 S 22 (d. B) -19 NA -14. 5 [3] ‘A 5 -GHz Fully Integrated ESD-Protected Low-Noise Amplifier in 90 -nm RF CMOS’, IEEE journal of solid state circuits, Dimitri Linten et. al, VOL. 40 No. 7 JULY 2005. [4] ‘A 90 -nm CMOS Two-Stage Low-Noise Amplifier for 3 -5 -GHz Ultra-Wideband Radio’ , Radio Frequency Integrated Circuits Symposium 2008, p 489 – 492. 4/27/2009 14

Conclusion and Future work �The current re-use technique will enable bias current sharing between two amplifier stages. �This in turn reduces the power dissipated in the circuit and hence the energy consumption. �Noise matching at the input port can be improved to get a better NF. �LNA for 60 GHz and above with low power design. �The transistor stages are stacked in the work here, we can find the optimum number of transistor stages that can be stacked for a constant power supply ‘Vdd’ and find gain and power consumption values for each increase in the stage. 4/27/2009 15

References �http: //bwrc. eecs. berkeley. edu/Research/RF/projects/60 GHz/ma tching/Imp. Match. html for impedance matching. �Introduction to LNA Design, queen’s learning wiki. http: //bmf. ece. queensu. ca/mediawiki/index. php/Introduction_to _LNA_Design �RF Microelectronics by B Razavi, Prentice Hall Communications Engineering and Emerging Technologies Series. �Radio Frequency Electronics by Jon B Hagen, Cambridge University Press. �‘ 60 -GHz PA and LNA in 90 -nm RF-CMOS’, Yao T et. al, Radio Frequency Integrated Circuits Symposium, 2006, IEEE, 4 pp. 4/27/2009 16

Questions 4/27/2009 17