LOGO An Analog PLLbased Technique for VCO Phase

LOGO An Analog PLL-based Technique for VCO Phase Noise Reduction D. Mavridis, D. Karadimas, M. Papamichail, K. Efstathiou, G. Papadopoulos University of Patras, Greece

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Contents 1 Phase Noise Reduction by Frequency Synthesizers. 2 Analysis of the Technique 3 Simulation Results 4 Conclusion 2 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com VCO’s Phase Noise Reduction in Frequency Synthesizers v Control Variable is the Phase v Phase Noise reduction due to the negative feedback 3 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Phase Noise Reduction by PLL (1) (2) Increasing ωn: (++) Phase Noise reduction increases (- - ) Spurs increase 4 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Key point v Increase Sampling rate: § Phase Information over a wide Bandwidth § Quantization Noise at very high frequencies § Large ωn values can be obtained => Increased Phase Noise Reduction 5 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Block Diagram Variable Mapping Freq. Synthesizer CCO Fstep (Hz) Iref(A) Φstep (rad) ∫Iref Fout( Hz) Φout (rad) (1) (2) (3) (4) (5) 6 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com CCO dynamics Transfer Function (1) (2) (3) 7 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Properties of the CCO v Very high sampling rate of the VCO’s phase § Reject the VCO’s Phase Noise for a wide bandwidth § Increased Phase Noise Rejection v CCO’s gain is not dependent on VCO’s gain v Fast response v CCO ->VCO using a simple transconductance 8 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Simulation Setup Technology: AMS 035 – CMOS Noisy VCO: Ring Oscillator (1) (2) (3) 9 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Simulation Results Free Run VCO ζ=0. 7 fn=20 MHz, Np=4 fsample=250 MHz ζ=0. 5 fn=40 MHz, Np=2 fsample=500 MHz 10 Company Logo

An Analog PLL-based Technique for VCO Phase Noise Reduction – Mavridis et al. www. themegallery. com Conclusion v Technique based on PLL § Negligible circuitry § Small Power overhead § Small chip area 11 Company Logo

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