Logic Simulator for Combinational Circuit Jie Qin Dept
Logic Simulator for Combinational Circuit Jie Qin Dept. of Electrical and Computer Engineering Auburn University, AL 36849, USA 04/25/2006 ELEC 7250 Final Project: Jie Qin 1
Problem Statement ► Develop a logic simulator with support for the standard bench format and the hierarchical bench format. ► When the output of the simulated circuit does not match the expected response, try to diagnose the error in the circuit using the logic simulator. 04/25/2006 ELEC 7250: Jie Qin 2
Logic Simulator ► The implemented logic simulator consists of a compiler and a simulator. -- the compiler reads in a circuit description in bench format and builds a simulation table in memory. -- the simulator propagates the values provided from outside at the PIs to the POs utilizing the simulation table (logic propagation). 04/25/2006 ELEC 7250: Jie Qin 3
Simulation Table ►A simulation table is actually ID a list of gate records. All the Name PIs, gates and POs in a circuit Class are represented by the gate Fanin list (FIL) records in the implemented logic simulator. A gate record Fanout list (FOL) includes the following Fanin’s value (FIV) information. Gate’s value (GV) 04/25/2006 ELEC 7250: Jie Qin 4
An Example of Simulation Table before logic propagation a d e f gate “d” gate “e” PI “a” PO “f” ID: 1 ID: 2 ID: 3 ID: 4 Name: d Name: e Name: a Name: f Class: AND Class: NOT Class: PI Class: PO FIL: {a, a} FIL: {d} FIL: {a} FIL: {e} FOL: {f} FOL: {d} FOL: {f} FIV: {-1, -1} FIV: {-1} GV: {-1} 04/25/2006 ELEC 7250: Jie Qin 5
Logic Propagation ► To propagate the known value at the PIs to the POs, two lists are maintained in the memory. -- passive list: it includes all the “gate records” whose outputs are in unknown states. -- active list: once a gate has its output in known state, it will be append to this list. However, after all the fanouts of this gate are determined as a known value, it will be removed from this list. 04/25/2006 ELEC 7250: Jie Qin 6
An Example of Logic Propagation a b 0 1 c 0 1 d 0 0 0 e 1 1 h Half-Adder active list passive list a b 04/25/2006 1 1 f g ELEC 7250: Jie Qin c d e f g h 7
Results for a 4 -bit Ripple Adder 04/25/2006 ELEC 7250: Jie Qin 8
Results for ISCAS’ 85 Circuits 04/25/2006 ELEC 7250: Jie Qin 9
Fault Diagnosis Assumption #1: the internal state of the CUT cannot observed from the outside ► Assumption #2: the possibility of single fault is much higher than multiple faults ► Approach: -- Step #1: for each faulty PO, obtain a reversed logic cone from PO; -- Step #2: intersect the logic cones obtained in Step #1; -- Step #3: try more test vectors to obtain a logic cone as small as possible. ► 04/25/2006 ELEC 7250: Jie Qin 10
Conclusion ► The execution time increases with the number of gates and the number of test vectors. ► The fault diagnosis still needs to be improved because the assumption does not match the real situation very well. 04/25/2006 ELEC 7250: Jie Qin 11
Thank you! 04/25/2006 ELEC 7250: Jie Qin 12
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