Logic design of asynchronous circuits Part II Logic

Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications 1

Outline • • • Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit – Complex gates – C-element architecture ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 2

Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 3

Specification x y x z y z z+ x+ xy+ z- y. Signal Transition Graph (STG) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 4

Token flow x y z z+ x+ xy+ z- y- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 5

State graph xyz 000 x+ z+ xy+ y- z- y- x- 001 y+ 100 y+ 101 110 y+ z+ 011 111 x- z- 010 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 6

Next-state functions xyz 000 x+ z+ y- x- 001 y+ 100 y+ 101 110 y+ z+ 011 111 x- z- 010 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 7

Gate netlist x y z ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 8

Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 9

VME bus Bus DSr Data Transceiver LDS Device D DSr DSw LDS VME Bus Controller LDTACK D DTACK Read Cycle ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 10

STG for the READ cycle DSr+ LDS+ LDTACK+ DTACK- D+ DTACK+ LDTACK- DSr- D- LDS- D DSr DTACK VME Bus Controller LDS LDTACK ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 11

Choice: Read and Write cycles LDTACK- LDS- DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ DTACK- LDTACK+ D- DSr- DTACK+ D- DSw- LDTACK- LDS- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 12

Choice: Read and Write cycles LDTACK- LDS- DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ DTACK- LDTACK+ D- DSr- DTACK+ D- DSw- LDTACK- LDS- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 13

Choice: Read and Write cycles LDTACK- LDS- DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ DTACK- LDTACK+ D- DSr- DTACK+ D- DSw- LDTACK- LDS- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 14

Choice: Read and Write cycles LDTACK- LDS- DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ DTACK- LDTACK+ D- DSr- DTACK+ D- DSw- LDTACK- LDS- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 15

Circuit synthesis • Goal: – Derive a hazard-free circuit under a given delay model and mode of operation ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 16

Speed independence • Delay model – Unbounded gate / environment delays – Certain wire delays shorter than certain paths in the circuit • Conditions for implementability: – Consistency – Complete State Coding – Persistency ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 17

Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 18

STG for the READ cycle DSr+ LDS+ LDTACK+ DTACK- D+ DTACK+ LDTACK- DSr- D- LDS- D DSr DTACK VME Bus Controller LDS LDTACK ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 19

Binary encoding of signals DSr+ LDS+ LDTACKDSr+ LDS- LDTACK+ DSr+ D+ DTACK- LDTACK- DTACKLDS- DTACK- DDTACK+ DSr- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 20

Binary encoding of signals DSr+ 10000 LDS+ LDTACK- DSr+ 10010 LDS- LDTACK+ DTACKLDS- DSr+ 10110 D+ DTACK- LDTACK- 01100 LDS- DTACK- 01110 00110 10110 DDTACK+ DSr- (DSr , DTACK , LDS , D) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 21

Excitation / Quiescent Regions ER (LDS+) LDS+ QR (LDS-) LDS- QR (LDS+) LDS- ER (LDS-) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 22

Next-state function 0 1 LDS+ 1 1 10110 0 0 LDS- 1 0 10110 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 23

Karnaugh map for LDS = 1 LDS = 0 D LDTACK DSr 00 01 11 10 00 0 0 - 1 00 - - - 1 01 - - - - 11 - 1 10 0 0 - 0/1? ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 24

Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 25

Concurrency reduction DSr+ LDS+ DSr+ LDS- DSr+ 10110 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 26

Concurrency reduction DSr+ LDS+ LDTACK+ D+ LDTACK- DTACK+ DSr- D- LDS- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 27

State encoding conflicts LDS+ LDTACK- LDS- 10110 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 28

Signal Insertion CSC+ LDS+ LDTACK- LDS- 101101 101100 D- DSr- CSC- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 29

Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 30

Complex-gate implementation ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 31

Implementability conditions • Consistency – Rising and falling transitions of each signal alternate in any trace • Complete state coding (CSC) – Next-state functions correctly defined • Persistency – No event can be disabled by another event (unless they are both inputs) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 32

Implementability conditions • Consistency + CSC + persistency • There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 33

Persistency 100 a- 000 c+ 001 b+ b+ a c b is this a pulse ? Speed independence glitch-free output behavior under any delay ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 34

a+ 0000 a+ b+ 1000 b+ 1100 a- a- 0100 c+ c+ 0110 d+ d+ 0111 a+ a+ 1111 b- ba- 1011 cd- d- a- 0011 c- a- c- 1001 0001 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 35

cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 b+ 1100 1 0000 10 1 1 1 a- 0100 ER(d+) c+ 0110 d+ 10 d- 0111 1 a+ 1111 b- 1011 a- 0011 ER(d-) c- a- c- 1001 0001 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 36

cd ab 00 01 11 00 0 01 0 11 0 0 1 10 1 1 1 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d+ 10 1 d- 0111 a+ 1111 b- 1011 a- 0011 Complex gate c- a- c- 1001 0001 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 37

Implementation with C elements S R C z • • • S+ z+ S- R+ z- R- • • S (set) and R (reset) must be mutually exclusive • S must cover ER(z+) and must not intersect ER(z-) QR(z-) • R must cover ER(z-) and must not intersect ER(z+) QR(z+) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 38

cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 b+ 1100 1 0000 10 1 a- 0100 c+ 1 1 0110 d+ 10 d- 0111 1 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 39

0000 a+ 1000 b+ 1100 but. . . a- 0100 c+ 0110 d+ d- 0111 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 40

Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): 0000 a+ 1000 b+ 1100 a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; a- 0100 c+ R+ disabled (potential glitch) 0110 d+ d- 0111 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 41

cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 b+ 1100 1 0000 10 1 a- 0100 c+ 1 1 0110 d+ 10 d- 0111 1 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 ASPDAC / VLSIcovers 2002 - Tutorial on Logic Design of Asynchronous Circuits Monotonic 42

C-based implementations S R c a b c d C C b a d weak d c weak d a generalized C elements (g. C) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 43

Speed-independent implementations • Implementability conditions – Consistency – Complete state coding – Persistency • Circuit architectures – Complex (hazard-free) gates – C elements with monotonic covers –. . . ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 44

Synthesis exercise y- 1001 z- zy+ wx+ z+ w+ x- y+ 1010 1000 w- w- z- w- y+ 0010 y- 0000 x+ w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 1011 z+ 0111 Derive circuits for signals x and z (complex gates and monotonic covers) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 45

Synthesis exercise yz wx 1001 z 00 01 11 10 00 1 1 - 0 y+ 01 1 1 - 0 1010 11 0 0 - 0 10 1 1 - 0 1000 w- w- z- w- y+ 0010 y- 0000 x+ w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 1011 z+ 0111 Signal x ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 46

Synthesis exercise yz wx 1001 z 00 01 11 10 00 0 0 - 0 y+ 01 0 0 - 0 1010 11 1 1 - 1 10 0 1 - 0 1000 w- w- z- w- y+ 0010 y- 0000 x+ w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 1011 z+ 0111 Signal z ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 47