Logic Circuits and Standard Cells September 27 2006

Logic Circuits and Standard Cells September 27, 2006

Static CMOS has two ‘sources’ to switch-connect to output PMOS is on with –ve Vgs

S=(B+C)(AC+AD) Less contact -> Less cap, area-> High speed, Low power

Transmission gate-based logic 1. Input can be applied to source(drain) as well as gate. 2. Therefore, # of transistors can be smaller than static CMOS, 3. But not necessarily the area, as there are more butting contacts between NMOS and PMOS Only by NMOS By both NMOS and PMOS, as d can be 0 or 1

Single pass-transistor logic (SPL) 1. Need restorer for high-value at the output 2. Good for high Vdd; Inferior to static CMOS in speed and power for low Vdd CPL(Complementary Pass Transistor Logic)

CPL(Complementary Pass Transistor Logic) • Still ratioed logic, although PMOS part cross-coupled connection incurs regenerative action. • Different from DCVSL (Differential Cascode Voltage Logic) as DCVSL has source of NMOS grounded. • Faster than static CMOS with 3. 3 V but slower with 1. 2 V Vdd.

Relation between low power and high speed • • t=CVdd/Ids Reducing V Reducing C Athlete breathes less at normal time.

NORA ; Output is latched at the beginning of evaluation (PR=0)

Using lower freq. lowers power in the clock tree

Must not be included in the logic optimization