Little and bigendian memory organizations 2000 Addison Wesley
Little- and big-endian memory organizations © 2000 Addison Wesley
ARM operating modes and register usage. © 2000 Addison Wesley
Exception vector addresses © 2000 Addison Wesley
The ARM condition code field © 2000 Addison Wesley
ARM condition codes © 2000 Addison Wesley
Branch and Branch with Link binary encoding © 2000 Addison Wesley
Branch (with optional link) and exchange instruction binary encoding (1) BX|BLX Rm 31 2827 6 5 4 3 0001001011111100 cond L 1 0 Rm (2) BLX label 31 2827 2524 23 1111 101 H © 2000 Addison Wesley 0 24 -bit signed word offset
Software interrupt binary encoding © 2000 Addison Wesley
Data processing instruction binary encoding 31 28 2726 25 24 cond 21 20 19 0 0 # opcode S 1615 Rn 12 11 0 operand 2 Rd destination register first operand register set condition codes arithmetic/logic function 25 11 8 7 #rot 1 0 8 -bit immediate alignment 11 7 6 5 4 3 #shift 25 immediate shift length 0 shift type Sh 0 0 Rm second operand register 11 8 7 6 5 4 3 Rs register shift length © 2000 Addison Wesley 0 Sh 1 0 Rm
ARM data processing instructions © 2000 Addison Wesley
Multiply instruction binary encoding © 2000 Addison Wesley
Multiply instructions © 2000 Addison Wesley
Count leading zeros instruction binary encoding © 2000 Addison Wesley
Single word and unsigned byte data transfer instruction binary encoding © 2000 Addison Wesley
Half-word and signed byte data transfer instruction binary encoding © 2000 Addison Wesley
Data type encoding © 2000 Addison Wesley
Multiple register data transfer instruction binary encoding © 2000 Addison Wesley
Swap memory and register instruction binary encoding © 2000 Addison Wesley
Status register to general register transfer instruction binary encoding © 2000 Addison Wesley
Transfer to status register instruction binary encoding 31 28 27 26 25 24 23 22 21 20 19 cond 00 # 10 R 10 16 15 field 12 11 0 operand 1111 field mask SPSR/CPSR 25 11 1 8 7 #rot 0 8 -bit immediate alignment 25 11 0 0000 operand register © 2000 Addison Wesley 4 3 0 Rm
Coprocessor data processing instruction binary encoding © 2000 Addison Wesley
Coprocessor data transfer instruction binary encoding © 2000 Addison Wesley
Coprocessor register transfer instruction binary encoding © 2000 Addison Wesley
Breakpoint instruction binary encoding © 2000 Addison Wesley
Arithmetic instruction extension space © 2000 Addison Wesley
Control instruction extension space © 2000 Addison Wesley
Data transfer instruction extension space © 2000 Addison Wesley
Coprocessor instruction extension space © 2000 Addison Wesley
Undefined instruction space © 2000 Addison Wesley
Summary of ARM architectures Core Architecture ARM 1 v 1 ARM 2 v 2 ARM 2 as, ARM 3 v 2 a ARM 6, ARM 600, ARM 610 v 3 ARM 7, ARM 700, ARM 710 v 3 ARM 7 TDMI, ARM 710 T, ARM 720 T, ARM 740 T v 4 T Strong. ARM, ARM 810 v 4 ARM 9 TDMI, ARM 920 T, ARM 940 T v 4 T ARM 9 ES v 5 TE ARM 10 TDMI, ARM 1020 E v 5 TE © 2000 Addison Wesley
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