LHCb Outer Tracker Upgrade Actel FPGA based Architecture

LHCb Outer Tracker Upgrade Actel FPGA based Architecture Outline ◦ ◦ ◦ Front end box Architecture Actel TDC Data GBT interface Data format Test Setup AMC 40 test setup 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 1

Front-end box architecture 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 2

Front-end box ◦ 1 GBT master/power board (replaces: GOL board) Versatile link transceiver, <-> Master GBT TFC signals 1 SCA for monitoring (power, temperature, etc. ) 8 Optical data transmitters 4 dual transmitters versatile link OR 12 -way optical transmitter, based on KK Ghan’s vcsel driver (8+4 spare) Power supplies based on CERN SM 01 C DC/DC conv. ◦ 4 Actel TDC boards (replaces: OTIS boards) 2 data transmitter GBT’s Wide bus format data transmitters One used for clocks, Bx. Clk Tp. Clk, TFC, clk Spare clocks for TDC 1 SCA Actel re-programming via JTAG GBT configuration 4 Threshold DAC Temperature monitoring Soft reset Actel 1 Actel Pro-asic A 3 PE 1500 32 channel, 5 -bits TDC Zero suppression ◦ 8 ASDBLR boards (unchanged) 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 3

Actel TDC Pro-Asic A 3 PE 1500 (4 32 channel 5 bits TDC FPGA’s/FE-box) ◦ Based on 4 320 MHz clocks(2 edges and 90 phase shifted) ◦ fixed placement (3 variants: top right bottom) Zero suppression 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 4

Data GBT interface Two options uses identical PCB, different Actel firmware ◦ 8 Data GBT’s per FE-box One ZS output bus per 16 channels No bandwidth limitations NZS full bandwidth readout possible ◦ 4 data GBT’s per FE-box One ZS output bus per 32 channels Bandwidth limit, lower cost Wide-bus GBT format 28 b@160 MHz 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 5

Two 16 ch. TDC in one FPGA Dual GBT’s 16 channel TDC Zero-supp 16 stages Fifo Readout GBT 1 16 channel TDC Zero-supp 16 stages Fifo Readout GBT 2 Actel FPGA Data Format (9 channels hit): GBT 1 27 16 bits Hit pattern channel (0 -15) Padded ‘ 0’ 5 bits Data 0 4 bits BX cnt 5 bits Data Padded ‘ 0’ 5 bits Data Max 4 words when all channels are hit GBT 2 16 bits Hit pattern channel (16 -31) 5 bits Data 8 bits Status 4 bits BX cnt 5 bits Data 8 bits Status 5 bits Data Max 4 words when all channels are hit 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 6

32 channel TDC with single GBT 32 channel TDC Zero-supp 32 stages Fifo Readout GBT Actel FPGA Data Format (9 channels hit): GBT 27 16 bits Hit pattern channel (0 -15) Data 5 bits Data 0 4 bits BX cnt 8 bits Status 16 bits Hit pattern channel(16 -31) 5 bits Data Padded ‘ 0’ s 5 bits Data 5 bits Dat Max 8 words when all channels are hit 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 7

OTTOv 2 Test Setup Stratix. IV 230 evaluation board Dummy GBT, based on code Sophie baron Not yet implemented Small TFC Data buffer (512 MB DDR 3) I 2 C over Ethernet, dummy ECS/SCA OT TDC to Optical: OTTOv 2 Prototype board with combined TDC board (OTIS) and Master GBT board (GOL) Actel TDC Snap 12 optical receiver/transmitter Versatile link: Dual transmitter (data GBT) Bi-directional (master GBT) SM 01 C radiation hard DC/DC power converters SCA Mezzanine (SCA pin-out not known) Threshold DAC 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 8

Test setup 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 9

Test Setup Altera Dummy GBT slave Altera Dummy GBT master 1 Gb. Eth Actel TDC ASDBLR left 17 januari 2013 1 Gb. Eth Snap 12 Rx Snap 12 Tx SCA Vers. Link Power ASDBLR right Antonio Pellegrino, Tom Sluijk, Wilco Vink, 10

Test setup with AMC 40 OTTO with master/slave Stratix. IV ◦ Data GBT emulated ◦ Master GBT TFC signals ECS via E-Link to SCA ◦ dev. brd as 1/4 Front end box ◦ Needs GBT wide-bus FPGA code (S. Baron) AMC 40 used for DAQ and TFC/ECS ◦ Needs AMC 40 firmware TFC/ECS OT data format, DAQ interface to 10 Gb. E ◦ PC control software available? ECS/TFC (PVSS <-> CCPC <-> GBT <-> SCA <-> OTTO) DAQ->data-storage 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 11

AMC 40 test setup overview 17 januari 2013 Antonio Pellegrino, Tom Sluijk, Wilco Vink, 12