LFB LLRF TFB update Alessandro Drago XIII Super

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LFB, LLRF, TFB update Alessandro Drago XIII Super. B General Meeting Isola d’Elba, 5/30

LFB, LLRF, TFB update Alessandro Drago XIII Super. B General Meeting Isola d’Elba, 5/30 -6/4 2010

Topics • Longitudinal dynamics simulator: beam + RF + LFB • • • Longitudinal

Topics • Longitudinal dynamics simulator: beam + RF + LFB • • • Longitudinal growth rate evaluation Power amplifiers evaluation LLRF update Transverse dynamics simulator Hardware update

Feedback design basic points • Hardware refresh (to avoid obsolescence) • Legacy/diagnostics from the

Feedback design basic points • Hardware refresh (to avoid obsolescence) • Legacy/diagnostics from the previous feedback systems • Unified project for transverse and longitudinal systems • Evaluation of feedback impact on ultra-low emittance beams • Signal/noise ratio (included crosstalk from other bunches) of the order of ~40 d. B • System dynamic range of the order of ~75/80 d. B

Poster presented at IPAC 2010 Kyoto May, 2010

Poster presented at IPAC 2010 Kyoto May, 2010

Data base in SIMUL 2 longitudinal simulator are: RF power, 11 HOM in RF

Data base in SIMUL 2 longitudinal simulator are: RF power, 11 HOM in RF cavities, beam paramenters (charge x bunch, harmonic number, #bunches, gap, injection error) and Longitudinal feedback parameters (gain, power, FIR transfer function with coefficients)

The longitudinal simulator upgrade • MATLAB program have been upgraded and rewritten to make

The longitudinal simulator upgrade • MATLAB program have been upgraded and rewritten to make a fast data entry and also to measure growth and damping rate from the raw output data

Baseline

Baseline

LER High Current

LER High Current

Summary of long. growth rates • 4 A in 1956 bunches generates at every

Summary of long. growth rates • 4 A in 1956 bunches generates at every new charge injection very fast instability • Injecting bunch #2 the instability growth rates are faster in the nearby bunches than in the others along the bunch train • Bunch #11 178 turns, 0. 75 msec • Bunch #1225 673 turns, 2. 82 msec • Bunch #1955 691 turns, 2. 93 msec

High current case (4 A), bunches spaced by 1: lfb needs a total power

High current case (4 A), bunches spaced by 1: lfb needs a total power of 1 k. W, implemented by four 250 W amplifiers feeding one cavity kicker with Rs>500 Ohm. This power should be sufficient to control the beam longitudinal dynamics at 4 A in LER

LLRF - Low Level RF System description (from CDR 2 by Sacha Novokhatski) •

LLRF - Low Level RF System description (from CDR 2 by Sacha Novokhatski) • A low-level RF system provides control and feedback for stable multibunch high current operation. There are several feedback loops. BLOCK DIAGRAM OF LLRF CIRCUITS

LLRF update by the Grenoble Team in the next Super. B General Meeting

LLRF update by the Grenoble Team in the next Super. B General Meeting

Transverse model with FPGA code

Transverse model with FPGA code

Beam transfer function [transverse resistive wall instability] • Grate = modal instability hypothetical growth-rate

Beam transfer function [transverse resistive wall instability] • Grate = modal instability hypothetical growth-rate [from real example: DAFNE or CESR-TA] • In DAFNE, the e+ ring fastest measured Grate is ~20 revolution turns • Wx = angular betatron tune frequency [2*pi*betatron_tune_fractional_part*rev_freq] • G = gain (function of impedances & wakefields, RF_frequency^2, bunch_spacing, …) - in the preliminary phase is put to 1

C. S. N. V approves SFEED in Sept/09 • Only for the year 2010

C. S. N. V approves SFEED in Sept/09 • Only for the year 2010 • 2 K euro for mission outside Italy • 16 k euro for hardware/software and assembly

Finally a Virtex-6 FPGA evaluation board is now on sale: Xilinx ML 605

Finally a Virtex-6 FPGA evaluation board is now on sale: Xilinx ML 605

Finally a Virtex-6 FPGA evaluation board is now on sale • Xilinx ML 605

Finally a Virtex-6 FPGA evaluation board is now on sale • Xilinx ML 605 – similar to previous project based on Virtex-5 • Part number AES-V 6 DSP-LX 240 T-G • http: //www. xilinx. com/products/devkits/AESV 6 DSP-LX 240 T-G. htm • Expensive cost: 2995 $ + VAT cointaining • Xilinx ML 605 Development Board including Virtex-6 LX 240 T FPGA. • http: //www. xilinx. com/products/devkits/EK-V 6 ML 605 -G. htm • Only the board: 1995 $ +VAT.

14 bit ADC / 16 bit DAC • • • ADC (analog input signal):

14 bit ADC / 16 bit DAC • • • ADC (analog input signal): ADS 5474 by. Texas Instruments, [14 -bit, 400 MSPS] http: //focus. ti. com/lit/ds/symlink/ads 5474. pdf It has 14 differential digital output LVDS on a unique register then better than the previous project that was using 16 digitalc output beacasuse was based on 2 registers ADS 5474 has an evaluation board: http: //focus. ti. com/lit/ug/slau 194 a. pdf DAC: Maxim MAX 5891 http: //www. maximic. com/quick_view 2. cfm/qv_pk/4622 16 -Bit, 600 Msps High-Dynamic Performance DAC with LVDS Inputs and DAC evaluation board: http: //datasheets. maxim-ic. com/en/ds/MAX 5889 EVKIT-MAX 5891 EVKIT. pdf The evalutation board has 16 differential LVDS input with a single connettor while clock and analog output signal are SMA

14 bit ADC / 16 bit DAC • It is necessary to assembly 3

14 bit ADC / 16 bit DAC • It is necessary to assembly 3 boards designing an interface board connecting all the evaluation boards ( [email protected] bit, FPGA with Virtex-6, [email protected] bit). • The software, firmware and gateware for the FPGA board ML 605 should be also designed

14 bit ADC / 16 bit DAC • An order for these 3 boards

14 bit ADC / 16 bit DAC • An order for these 3 boards has still NOT signed by LNF top management (I am waiting since more than 1 month) • Why? ? ?

DIMTEL order • An order to DIMTEL has made in last January for two

DIMTEL order • An order to DIMTEL has made in last January for two longitudinal front end modules and two 12 -bit ADC processing unit • It is an upgrade from IGP to IGP-12 • It is based on Virtex-5 not on Virtex-6 • The order is in progress and we are still waiting for the material • Material is sold as a black box (no info about code)