Lesson 4 Just like LEGO The NAND gate

Lesson 4: “Just like LEGO” The NAND gate “Reading” CMOS gates Designing CMOS gates

Logic

NAND 2 -inputs “Gates are inverters in disguise!” Paulo Moreira Gates 3

NAND 3 -inputs Paulo Moreira Gates 4

NAND 3 -inputs Paulo Moreira Gates 5

NAND: Switching Time, Propagation Delay t. Low 2 High= Rp/N (N*Cout, p+Cout, n/N+Cload) t. High 2 Low= N*Rn (Cout, n/N+N*Cout, p+Cload) Gate Delay=1/2*(t. L 2 H+ t. H 2 L) n, p : n-channel, p-channel transistors. Rp, Rn: Ron of respective transistors. N = number of Inputs.

Estimation of Gate Delay: Gate Delay = K 1(p. Sec) +K 2 (p. Sec*um/f. F)* Cload / Wn Wn=Width of n-channel FET (Wp/Wn=constant) K 1 & K 2 determined from spice simulation of cascaded inverters. Wp/Wn K 1 K 2 1 39 12. 8 2 38 8. 78 3 41 6. 35 When FETs in series, the effective W is respectively smaller. Cload calculated from Fan-out * Capacity(per Gate) + Capacity of Line.

NAND 3 -inputs Paulo Moreira Gates 8

NAND 3 -inputs Paulo Moreira Gates 9

“Reading” CMOS gates Paulo Moreira Gates 10

Designing CMOS gates Paulo Moreira Gates 11

Complex CMOS gates • Can a compound gate be arbitrarily complex? – NO, propagation delay is a strong function of fan-in: – FO Fan-out, number of loads connected to the gate: • 2 gate capacitances per FO + interconnect – FI Fan-in, Number of inputs in the gate: • Quadratic dependency on FI due to: – Resistance increase – Capacitance increase – Avoid large FI gates (Typically FI 4) Paulo Moreira Gates 12

NAND: Switching Point VSP=(bn / (N*bp))^1/2*VT, n+(VDD-VT, p) -------------------1+(bn / (N*bp))^1/2 N = number of Inputs. n, p : n-channel, p-channel transistors.