Lecture No 21 Programmable Logic Devices Recap n

Lecture No. 21 Programmable Logic Devices

Recap n n n PLA Device Implementing 0 and 1 Implementing Odd-Prime Number GAL Operation EECMOS cells Programming PLDs

Recap n n GAL 22 V 10 OLMC n n Combinational Mode Registered Mode

GAL 16 V 8 n Emulate PALs three modes n n n 8 inputs 2 special function inputs 8 outputs 8 sum-of-product terms Each has 8 product terms OLMC n n n Output control (4 options) Feedback control (3 options) OR gate output (programmed polarity)

GAL 16 V 8 n Simple Mode (3 options) n n Complex Mode (2 options) n n n Combinational Output (fig 1) Combinational o/p with feedback (fig 2) Dedicated Input (fig 3) Combinational o/p (fig 4) Combinational Input/output (fig 5) Registered Mode

ABEL n n n Acronym Advanced Boolean Expression Language ABEL Boolean Operators and Notations (tab 1, 2) Programming by Boolean expression n ABEL Boolean expression (fig 6) Defining multiple Inputs/Outputs (tab 3 fig 7) Defining sets (fig 8, 9)

ABEL n Programming by Truth Table n n Test Vectors n n XOR gate (fig 10) Comparator (fig 11) Comparator using sets (fig 12) Comparator (fig 13 14) ABEL Input File three sections n n n Declarations (device, pin, set) (fig 15) Logic Description Test Vectors

Implementing Quad MUX n n n Quad 1 -of-4 function table (tab 4) ABEL Input file for the MUX (fig 16) ABEL Implementation for MUX (fig 17)