Lecture 9 OUTLINE Transient response of 1 storder

Lecture #9 OUTLINE – Transient response of 1 st-order circuits – Application: modeling of digital logic gate Reading Chapter 4 through Section 4. 3 EECS 40, Fall 2004 Lecture 9, Slide 1 Prof. White

Transient Response of 1 st-Order Circuits • In Lecture 8, we saw that the currents and voltages in RL and RC circuits decay exponentially with time, with a characteristic time constant t, when an applied current or voltage is suddenly removed. • In general, when an applied current or voltage suddenly changes, the voltages and currents in an RL or RC circuit will change exponentially with time, from their initial values to their final values, with the characteristic time constant t: where x(t) is the circuit variable (voltage or current) xf is the final value of the circuit variable t 0 is the time at which the change occurs EECS 40, Fall 2004 Lecture 9, Slide 2 Prof. White

Procedure for Finding Transient Response 1. Identify the variable of interest • • For RL circuits, it is usually the inductor current i. L(t) For RC circuits, it is usually the capacitor voltage vc(t) 2. Determine the initial value (at t = t 0+) of the variable • Recall that i. L(t) and vc(t) are continuous variables: i. L(t 0+) = i. L(t 0 ) and vc(t 0+) = vc(t 0 ) • Assuming that the circuit reached steady state before t 0 , use the fact that an inductor behaves like a short circuit in steady state or that a capacitor behaves like an open circuit in steady state EECS 40, Fall 2004 Lecture 9, Slide 3 Prof. White

Procedure (cont’d) 3. Calculate the final value of the variable (its value as t ∞) • Again, make use of the fact that an inductor behaves like a short circuit in steady state (t ∞) or that a capacitor behaves like an open circuit in steady state (t ∞) 4. Calculate the time constant for the circuit t = L/R for an RL circuit, where R is the Thévenin equivalent resistance “seen” by the inductor t = RC for an RC circuit where R is the Thévenin equivalent resistance “seen” by the capacitor EECS 40, Fall 2004 Lecture 9, Slide 4 Prof. White

Example: RL Transient Analysis Find the current i(t) and the voltage v(t): R = 50 W t=0 i Vs = 100 V + + v L = 0. 1 H – 1. First consider the inductor current i 2. Before switch is closed, i = 0 --> immediately after switch is closed, i = 0 3. A long time after the switch is closed, i = Vs / R = 2 A 4. Time constant L/R = (0. 1 H)/(50 W) = 0. 002 seconds EECS 40, Fall 2004 Lecture 9, Slide 5 Prof. White

t=0 R = 50 W i Vs = 100 V + + v L = 0. 1 H – Now solve for v(t), for t > 0: From KVL, = 100 e-500 t volts` EECS 40, Fall 2004 Lecture 9, Slide 6 Prof. White

Example: RC Transient Analysis Find the current i(t) and the voltage v(t): R 1 = 10 k. W t=0 i Vs = 5 V + R 2 = 10 k. W + v C = 1 m. F – 1. First consider the capacitor voltage v 2. Before switch is moved, v = 0 --> immediately after switch is moved, v = 0 3. A long time after the switch is moved, v = Vs = 5 V 4. Time constant R 1 C = (104 W)(10 -6 F) = 0. 01 seconds EECS 40, Fall 2004 Lecture 9, Slide 7 Prof. White

R 1 = 10 k. W Vs = 5 V + R 2 = 10 k. W t=0 i + v C = 1 m. F – Now solve for i(t), for t > 0: A From Ohm’s Law, = 5 x 10 -4 e-100 t A EECS 40, Fall 2004 Lecture 9, Slide 8 Prof. White

EECS 40, Fall 2004 Lecture 9, Slide 9 Prof. White

EECS 40, Fall 2004 Lecture 9, Slide 10 Prof. White

Application to Digital Integrated Circuits (ICs) When we perform a sequence of computations using a digital circuit, we switch the input voltages between logic 0 (e. g. , 0 Volts) and logic 1 (e. g. , 5 Volts). The output of the digital circuit changes between logic 0 and logic 1 as computations are performed. EECS 40, Fall 2004 Lecture 9, Slide 11 Prof. White

Digital Signals We send beautiful pulses in: voltage We compute with pulses. But we receive lousy-looking pulses at the output: voltage time Capacitor charging effects are responsible! • Every node in a real circuit has capacitance; it’s the charging of these capacitances that limits circuit performance (speed) EECS 40, Fall 2004 Lecture 9, Slide 12 Prof. White

Circuit Model for a Logic Gate • Recall (from Lecture 1) that electronic building blocks referred to as “logic gates” are used to implement logical functions (NAND, NOR, NOT) in digital ICs – Any logical function can be implemented using these gates. • A logic gate can be modeled as a simple RC circuit: R + Vin(t) + C Vout – switches between “low” (logic 0) and “high” (logic 1) voltage states EECS 40, Fall 2004 Lecture 9, Slide 13 Prof. White

Logic Level Transitions Transition from “ 0” to “ 1” (capacitor charging) Transition from “ 1” to “ 0” (capacitor discharging) Vout Vhigh 0. 63 Vhigh 0. 37 Vhigh 0 RC time (Vhigh is the logic 1 voltage level) EECS 40, Fall 2004 Lecture 9, Slide 14 Prof. White

Sequential Switching Vin What if we step up the input, 0 time wait for the output to respond, Vin 0 Vout 0 time then bring the input back down? Vin 0 Vout 0 EECS 40, Fall 2004 Lecture 9, Slide 15 0 time Prof. White

Pulse Distortion R Vin(t) The input voltage pulse width must be large enough; otherwise the output pulse is distorted. + + Vout C – (We need to wait for the output to reach a recognizable logic level, before changing the input again. ) – 6 5 4 3 2 1 0 Pulse width = RC Vout 6 5 4 3 2 1 0 Pulse width = 10 RC 0 1 2 Time 3 EECS 40, Fall 2004 4 5 6 5 4 3 2 1 0 Vout Pulse width = 0. 1 RC 0 1 2 Time 3 Lecture 9, Slide 16 4 5 0 5 10 Time 15 20 25 Prof. White

Example Suppose a voltage pulse of width 5 ms and height 4 V is applied to the input of this circuit beginning at t = 0: t = RC = 2. 5 ms Vin R Vout C R = 2. 5 kΩ C = 1 n. F • First, Vout will increase exponentially toward 4 V. • When Vin goes back down, Vout will decrease exponentially back down to 0 V. What is the peak value of Vout? The output increases for 5 ms, or 2 time constants. It reaches 1 -e-2 or 86% of the final value. 0. 86 x 4 V = 3. 44 V is the peak value EECS 40, Fall 2004 Lecture 9, Slide 17 Prof. White

4 3. 5 3 2. 5 2 1. 5 1 0. 5 00 Vout(t) = EECS 40, Fall 2004 2 { 4 6 8 10 4 -4 e-t/2. 5 ms for 0 ≤ t ≤ 5 ms 3. 44 e-(t-5 ms)/2. 5 ms for t > 5 ms Lecture 9, Slide 18 Prof. White

EECS 40, Fall 2004 Lecture 9, Slide 19 Prof. White