Lecture 9 Memory Elements and Clocking Prith Banerjee

Lecture 9 Memory Elements and Clocking Prith Banerjee ECE C 03 Advanced Digital Design Spring 1998 ECE C 03 Lecture 9 1

Outline • • • Sequential logic networks Latches (RS Latch) Flip-flops (D and JK) Timing issues (setup and hold times) READING: Katz 6. 1, 6. 2, 6. 3, Dewey 8. 1, 8. 2 ECE C 03 Lecture 9 2

Sequential Switching Networks Circuits with Feedback: Some outputs are also inputs Traffic Light Controller is a complex sequential logic network Sequential logic forms basis for building "memory" into circuits These memory elements are primitive sequential circuits ECE C 03 Lecture 9 3

Simple Circuits with Feedback Primitive memory elements created from cascaded gates Simplest gate component: inverter Basis for commercial static RAM designs Cross-coupled NOR gates and NAND gates also possible "1" Cascaded Inverters: Static Memory Cell "0" LD LD A Selectively break feedback path to load new value into cell LD Z LD ECE C 03 Lecture 9 4

Inverter Chains 1 0 0 A B C D E X Odd # of stages leads to ring oscillator Snapshot taken just before last inverter changes Timing Waveform: tp = n * td n = # inverters Output high propagating thru this stage Period of Repeating Waveform (tp) Gate Delay (td) A (=X) 0 B 1 C 0 D 1 E 0 1 ECE C 03 Lecture 9 5

RS Latch Just like cascaded inverters, with capability to force output to 0 (reset) or 1 (set) R S R Q S Timing Waveform Reset Q Hold Set Reset Set 100 Race Forbidden State 6 R S Q Q Forbidden ECE C 03 Lecture 9 State

State Behavior of RS Latch Q Q 0 1 Q Q 1 0 Q Q 0 0 Truth Table Summary of R-S Latch Behavior Q Q 1 1 ECE C 03 Lecture 9 7

Theoretical RS Latch State Diagram SR = 00, 10 SR = 00, 01 SR = 1 0 Q Q 0 1 Q Q 1 0 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 Q Q 0 0 SR = 0 1 SR = 1 0 SR = 0 0, 11 Q Q 1 1 ECE C 03 Lecture 9 8

Observed RS Latch Behavior SR = 00, 10 SR = 00, 01 SR = 1 0 Q Q 0 1 Q Q 1 0 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 Q Q 0 0 SR = 0 0 Very difficult to observe R-S Latch in the 1 -1 state Ambiguously returns to state 0 -1 or 1 -0 A so-called "race condition" ECE C 03 Lecture 9 9

Definition of Terms in Clocking Tsu Th Clock: Periodic Event, causes state of memory element to change Input rising edge, falling edge, high level, low level Clock Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized Hold Time (Th) Minimum time after the clocking event during which the input must remain stable ECE C 03 Lecture 9 10

Level Sensitive RS Latch Level-Sensitive Latch Schematic: aka Gated R-S Latch S Q R Q enb Timing Diagram: S R enb Q Q ECE C 03 Lecture 9 11

Latches vs Flip-flops Input/Output Behavior of Latches and Flipflops Type When Inputs are Sampled When Outputs are Valid unclocked always propagation delay from latch input change level clock high propagation delay from sensitive (Tsu, Th around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) ECE C 03 Lecture 9 12

Latches vs Flipflops 7474 D Q Clk Positive edge-triggered flip-flop Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted Timing Diagram: 7476 D Q D C Clk Level-sensitive latch Bubble here for negative edge triggered device Clk Q 7474 Q 7476 Behavior the same unless input changes the clock is high ECE C 03 Lecture while 9 13

Timing Specifications of FFs 74 LS 74 Positive Edge Triggered D Flipflop D • Setup time • Hold time • Minimum clock width Clk • Propagation delays (low to high, high to low, max and typical) Q Tsu 20 ns Th 5 ns Tw 25 ns Tplh 25 ns 13 ns T su 20 ns Th 5 ns T phl 40 ns 25 ns All measurements are made from the clocking event that is, the rising edge of the clock ECE C 03 Lecture 9 14

Timing Specifications of Latches 74 LS 76 Transparent Latch D • Setup time • Hold time • Minimum Clock Width • Propagation Delays: high to low, low to high, maximum, typical data to output clock to output Clk Q T su Th 20 5 ns ns Tw 20 ns Tplh C» Q 27 ns 15 ns T plh D» Q 27 ns 15 ns Tsu 20 ns Th 5 ns T phl C» Q 25 ns 14 ns T phl D» Q 16 ns 7 ns Measurements from falling clock edge or rising or falling data edge ECE C 03 Lecture 9 15

RS Latch Revisited Truth Table: Next State = F(S, R, Current State) Derived K-Map: S(t) R(t) Q(t+d) Q( t ) 0 0 HOLD 0 0 1 1 ------------0 1 0 0 RESET 0 1 1 0 ------------1 0 0 1 SET 1 0 1 1 ------------1 1 0 X NOT ALLOWED 1 1 1 X SR S 00 01 11 10 0 X 1 1 1 0 X 1 R Characteristic Equation: Q+ = S + R Q t S R R-S Latch Q+ Q ECE C 03 Lecture 9 16

JK Flip Flop Design How to eliminate the forbidden state? K Q Q R-S latch J(t) K(t) Q(t+d) 0 0 HOLD 0 0 1 1 ------------0 1 0 0 RESET 0 1 1 0 ------------1 0 0 1 SET 1 0 1 1 ------------1 1 0 1 TOGGLE 1 1 1 0 R J S Q Q Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle Characteristic Equation: Q+ = Q K + Q J ECE C 03 Lecture 9 17

JK Latch Race Condition Set Reset 100 Toggle J K Q Q Race Condition Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop ECE C 03 Lecture 9 18

Solution: Master Slave JK Flip Flop Master Stage K Q R Slave Stage P R S Q R-S Latch J Q Q S P Q Q Clk Sample inputs while clock low Sample inputs while clock high Uses time to break feedback path from outputs to inputs! Set Reset 1's Catch Toggle 100 J K Clk P Master outputs P Q Q ECE C 03 Lecture 9 Slave outputs Correct Toggle Operation 19

Edge Triggered Flip Flops 1's Catching: a 0 -1 -0 glitch on the J or K inputs leads to a state change! forces designer to use hazard-free logic Solution: edge-triggered logic D D Negative Edge-Triggered D flipflop Holds D when clock goes low 4 -5 gate delays 0 R Q Clk=1 setup, hold times necessary to successfully latch the input Q S 0 D Holds D when clock goes low D Negative edge-triggered FF when clock is high ECE C 03 Lecture 9 Characteristic Equation: Q+ = D 20

Analysis of Edge-Triggered Flip Flops Step-by-step analysis D 0 D 4 3 D R Q Clk=0 D Q D S D' D 6 Q 5 Q S 2 D D D 1 D 0 D' ° D Negative edge-triggered FF when clock goes high-to-low data is latched Negative edge-triggered FF when clock is low data is held ECE C 03 Lecture 9 21

Positive vs Negative Edge Triggered Devices 100 D Clk Qpos Positive edgetriggered FF Qpos Qneg Negative edgetriggered FF Qneg Positive Edge Triggered Negative Edge Triggered Inputs sampled on rising edge Outputs change after rising edge Inputs sampled on falling edge Outputs change after falling edge Toggle Flipflop Formed from J-K with both inputs wired together ECE C 03 Lecture 9 22

Realizing Circuits with Different Kinds of FFs R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(In, Q, Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!! ECE C 03 Lecture 9 23

Realizing Circuits with Different Kinds of FFs Characteristic Equations R-S: Q+ = S + R Q Derived from the K-maps for Q+ = ƒ(Inputs, Q) D: Q+ = D J-K: Q+ = J Q + K Q T: Q+ = T Q + T Q E. g. , J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q Implementing One FF in Terms of Another D J C K Q Q Q K J D Q C Q D implemented with J-K ECE C 03 Lecture J-K implemented with D 9 24

Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Implementing D FF with a J-K FF: 1) Start with K-map of Q+ = ƒ(D, Q) 2) Create K-maps for J and K with same inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map E. g. , D = Q= 0, Q+ = 0 then J = 0, K = X ECE C 03 Lecture 9 25

Implementing JK FF with a D FF 1) K-Map of Q+ = F(J, K, Q) 2, 3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple! Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. ECE C 03 Lecture 9 26

Timing Methodology • Set of rules for interconnecting components and clocks • When followed, guarantee properation of system • Approach depends on building blocks used for memory elements For systems with latches: Narrow Width Clocking Multiphase Clocking (e. g. , Two Phase Non-Overlapping) For systems with edge-triggered flipflops: Single Phase Clocking • Correct Timing: (1) correct inputs, with respect to time, are provided to the FFs ECE C 03 Lecture 9 (2) no FF changes more than once per clocking event 27

Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register S, R are preset, preclear New value to first stage while second stage obtains current value of first stage IN D Q Q 0 C Q D Q Q 1 C Q CLK Correct Operation, assuming positive edge triggered FF ECE C 03 Lecture 9 28

Why Cascaded Flip-Flops Work • Propagation delays far exceed hold times; Clock width constraint exceeds setup time • This guarantees following stage will latch current value before it is replaced by new value • Assumes infinitely fast distribution of the clock In Tsu 20 ns Q 0 Q 1 Clk T plh 13 ns Th 5 ns ECE C 03 Lecture 9 Timing constraints guarantee properation of cascaded components 29

Narrow Width Clock vs Multiphase Clock Level Sensitive Latches vs. Edge Triggered Flipflops • Latches use fewer gates to implement a memory function • Less complex clocking with edge triggered devices Clk 2 (LD • Clk 1) A LD • Clk 1 Clk 2 CMOS Dynamic Storage Element Feedback path broken by two phases of the clock (just like master/slave idea!) Z 8 transistors to implement memory function but requires two clock signals constrained to be non-overlapping Edge-triggered D-FF: 6 gates (5 x 2 -input, 1 x 3 -input) = 26 transistors! ECE C 03 Lecture 9 30

Narrow Width Clocking for Systems with Latches Generic Block Diagram for Clocked Sequential System Combinational logic state implemented by latches or edge-triggered FFs S t a t e Clock Two-sided Constraints: must be careful of very fast signals as well as very slow signals! Clock Width < fastest propagation through comb. logic plus latch prop delay Clock Period > slowest propagation through comb. logic (rising edge to rising edge) ECE C 03 Lecture 9 31

Two Phase Nonoverlapping Clocks Clock Waveforms: must never overlap! only worry about slow signals Embedding CMOS storage element into Clocked Sequential Logic Combinational Logic 1 Combinational Logic 2 Note that Combinational Logic can be partitioned into two pieces C/L 1: inputs latched and stable by end of phase 1; compute between phases, latch outputs by end of phase 2 C/L 2: just the reverse ECE C 03 Lecture 9 32

Generating Two-Phase Non-Overlapping Clocks Single reference clock (or crystal) Phase 1 high while clock is low Phase 2 high while clock is high Phase X cannot go high until phase Y goes low! 100 Clk Phase 1 Phase 2 Non-overlap time can be increased by increasing the delay on the feedback path ECE C 03 Lecture 9 33

Problem of Clock Skew Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Not possible in real systems! • logical clock driven from more than one physical circuit with timing behavior • different wire delay to different points in the circuit Effect of Skew on Cascaded Flipflops: FF 0 samples IN In Q 0 FF 1 samples Q 0 100 CLK 2 is a delayed version of CLK 1 Q 1 Clk 2 Original State: Q 0 = 1, Q 1 = 1, In = 0 Because of skew, next state becomes: Q 0 = 0, Q 1 = 0, not Q 0 = 0, Q 1 = 1 ECE C 03 Lecture 9 34

Timing Methodologies Design Strategies for Minimizing Clock Skew Typical propagation delays for LS FFs: 13 ns Need substantial clock delay (on the order of 13 ns) for skew to be a problem in this relatively slow technology Nevertheless, the following are good design practices: • distribute clock signals in general direction of data flows • wire carrying the clock between two communicating components should be as short as possible • for multiphase clocked systems, distribute all clocks in similar wire paths; this minimizes the possibility of overlap • for the non-overlap clock generate, use the phase feedback signals from the furthest point in the circuit to which the clock is distributed; this guarantees that the phase is seen as low everywhere before it allows the next phase to go high ECE C 03 Lecture 9 35

Summary • • • Sequential logic networks Latches (RS Latch) Flip-flops (D and JK) Timing issues (setup and hold times) NEXT LECTURE: Registers and Counters READING: Katz 7. 1, 7. 2, 7. 4, 7. 5, Dewey 10. 2, 10. 3, 10. 4 ECE C 03 Lecture 9 36