Lecture 8 Arithmetic Logic Circuits Prith Banerjee ECE

Lecture 8 Arithmetic Logic Circuits Prith Banerjee ECE C 03 Advanced Digital Design Spring 1998 ECE C 03 Lecture 8 1

Outline • Review of Number Systems • Adders – Ripple carry – Carry Lookahead – Carry Select • • Combinational Multipliers Arithmetic and Logic Unit (ALU) General Logic Function Units READING: Katz 5. 2. 1, 5. 2. 2, 5. 2. 4, 5. 3, 5. 5, 4. 6 ECE C 03 Lecture 8 2

Review of Number Systems • Representation of positive numbers same in most systems • Differences in negative numbers • Three major schemes: – sign and magnitude – ones complement – twos complement • Assumptions: – we'll assume a 4 bit machine word – 16 different values can be represented – roughly half are positive, half are negative ECE C 03 Lecture 8 3

Sign Magnitude Number System High order bit is sign: 0 = positive (or zero), 1 = negative Three low order bits is the magnitude: 0 (000) thru 7 (111) Number range for n bits = +/-2 -1 n-1 Representations for 0 Cumbersome addition/subtraction ECE C 03 Lecture 8 Must compare magnitudes to determine sign of result 4

Twos Complement Representation like 1's comp except shifted one position clockwise Only one representation for 0 One more negative number than positive number ECE C 03 Lecture 8 5

Twos Complement Number System n N* = 2 - N 4 2 = 10000 Example: Twos complement of 7 sub 7 = 0111 1001 = repr. of -7 4 2 = 10000 Example: Twos complement of -7 sub -7 = 1001 0111 = repr. of 7 Shortcut method: Twos complement = bitwise complement + 1 0111 -> 1000 + 1 -> 1001 (representation of -7) 1001 -> 0110 + 1 -> 0111 (representation of 7) ECE C 03 Lecture 8 6

Addition and Subtraction of Numbers Sign and Magnitude result sign bit is the same as the operands' sign when signs differ, operation is subtract, sign of result depends on sign of number with the larger magnitude 4 0100 -4 1100 +3 0011 + (-3) 1011 7 0111 -7 1111 4 0100 -4 1100 -3 1011 +3 0011 1 0001 -1 1001 ECE C 03 Lecture 8 7

Twos Complement Addition and Subtraction Twos Complement Calculations 4 0100 -4 1100 +3 0011 + (-3) 1101 7 0111 -7 11001 If carry-in to sign = carry-out then ignore carry if carry-in differs from carry-out then overflow 4 0100 -4 1100 -3 1101 +3 0011 1 10001 -1 1111 Simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems ECE C 03 Lecture 8 8

Twos Complement Addition and Subtraction Why can the carry-out be ignored? -M + N when N > M: n n M* + N = (2 - M) + N = 2 + (N - M) Ignoring carry-out is just like subtracting 2 n -M + -N where N + M < or = 2 n-1 n n -M + (-N) = M* + N* = (2 - M) + (2 - N) n n = 2 - (M + N) + 2 After ignoring the carry, this is just the right twos compl. representation for -(M + N)! ECE C 03 Lecture 8 9

Circuits for Binary Addition Half Adder With twos complement numbers, addition is sufficient Half-adder Schematic ECE C 03 Lecture 8 10

Full Adder Cascaded Multi-bit Adder usually interested in adding more than two bits this motivates the need for the full adder ECE C 03 Lecture 8 11

Full Adder S = CI xor A xor B CO = B CI + A B = CI (A + B) + A B ECE C 03 Lecture 8 12

Full Adder Circuit Standard Approach: 6 Gates A B S CI CI CO A B Alternative Implementation: 5 Gates A B S A+B Half Adder. CO A B S A + B + CI Half Adder. CO CI (A + B) S CI + CO A B + CI (A xor B) = A B + B CI + A CI ECE C 03 Lecture 8 13

Adder/Subtractor A 3 B 3 A 2 B 2 0 1 Sel A B CO + CI A 1 B 1 0 1 Sel A B CO + A CI A 0 B 0 B CO + CI 0 1 Sel A B CO + S S S 3 S 2 S 1 S 0 CI Add/Subtract Overflow A - B = A + (-B) = A + B + 1 ECE C 03 Lecture 8 14

Delay Analysis of Ripple Adder • Carry out of a single stage can be implemented in 2 gate delays • For a 16 bit adder, the 16 th bit carry is generated after 16 * 2 = 32 gate delays. • The sum bit takes one additional gate delay to generate the sum of the 16 th bit after 15 th bit carry – 15 * 2 + 1 = 31 gate delays • Takes too long - need to investigate FASTER adders! ECE C 03 Lecture 8 15

Carry Lookahead Adder Critical delay: the propagation of carry from low to high order stages late arriving signal @0 @0 A B @1 @N+1 @N CI @0 @0 CO @N+2 A B @1 two gate delays to compute CO C 0 A 0 4 stage adder B 0 S 0 @2 0 A 1 B 1 C 1 @2 S 1 @3 1 A 2 B 2 C 2 @4 2 S 2 @5 C 3 @6 A 3 3 B 3 ECE C 03 Lecture 8 S 3 @7 C 4 @8 final sum and carry 16

Carry Lookahead Circuit Critical delay: the propagation of carry from low to high order stages S 0, C 1 Valid S 1, C 2 Valid S 2, C 3 Valid S 3, C 4 Valid 1111 + 0001 worst case addition T 0 T 2 T 4 T 6 T 8 T 0: Inputs to the adder are valid T 2: Stage 0 carry out (C 1) T 4: Stage 1 carry out (C 2) 2 delays to compute sum but last carry not ready until 6 delays later T 6: Stage 2 carry out (C 3) ECE C 03 Lecture 8 T 8: Stage 3 carry out (C 4) 17

Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here Sum and Carry can be reexpressed in terms of generate/propagate: Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi ECE C 03 Lecture 8 18

Carry Lookahead Logic Reexpress the carry logic as follows: C 1 = G 0 + P 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0! ECE C 03 Lecture 8 19

Carry Lookahead Implementation Ai Bi Pi @ 1 gate delay Ci Si @ 2 gate delays Gi @ 1 gate delay C 0 P 0 C 1 G 0 Increasingly complex logic C 0 P 0 P 1 P 2 P 3 G 0 P 1 P 2 C 0 P 1 G 0 P 1 Adder with Propagate and Generate Outputs C 2 G 1 P 2 C 3 G 0 P 1 P 2 P 3 G 2 G 1 C 4 G 2 P 3 ECE C 03 Lecture 8 G 3 20

Cascaded Carry Lookahead Logic C 0 Carry lookahead logic generates individual carries A 0 S 0 @2 B 0 C 1 @3 sums computed much faster A 1 S 1 @4 B 1 C 2 @3 A 2 S 2 @4 B 2 C 3 @3 A 3 S 3 @4 B 3 ECE C 03 Lecture 8 C 4 @3 21

Delay Analysis in Carry Lookahead • Assume a 4 -stage adder with CLA • Propagate and generate signals available after 1 gate delays • Carry signals for slices 1 to 4 available after 3 gate delays • Sum signal for slices 1 to 4 after 4 gate delays ECE C 03 Lecture 8 22

Carry Lookahead Logic Cascaded Carry Lookahead 4 4 4 C 16 A [15 -12] B[15 -12] C 12 4 -bit Adder P G 4 @8 S[15 -12] @2 @3 C 16 @5 P 3 C 4 G 3 4 4 A [11 -8] B[1 1 -8] 4 -bit Adder P G 4 @8 S[1 1 -8] @5 C 3 @2 @3 P 2 G 2 4 A [7 -4] B[7 -4] 4 -bit Adder P G 4 @7 C 8 S[7 -4] @5 C 2 @2 @3 P 1 G 1 Lookahead Carry Unit 4 4 A [3 -0] B[3 -0] 4 -bit Adder P G C 4 4 C 0 @0 @4 S[3 -0] @4 C 1 @2 @3 P 0 G 0 C 0 P 3 -0 @3 G 3 -0 C 0 @0 @5 4 bit adders with internal carry lookahead second level carry lookahead unit, extends lookahead to 16 bits ECE C 03 Lecture 8 23

Delay Analysis of Carry Lookahead • Consider a 16 -bit adder • Implemented with four stages of 4 -bit adders using carry lookahead • Carry in to the highest stage is available after 5 gate delays • Sum from highest stage available at 8 gate delays • COMPARE WITH 32 gate delays for a ripple carry adder • NOTE HOWEVER THIS ASSUMES ALL GATE DELAYS ARE SAME • Not true, delays depand on fan-ins and fan-out ECE C 03 Lecture 8 24

Carry Select Adder • Carry Select adder trades of more hardware for faster carry propagation • Basic idea is to break up 8 bit adder into two 4 -bit adder chunks • While the lowest significant 4 bit adder computes carry out • In parallel have TWO high-order 4 bit adders compute result with two possible cases – carry in of 0 – carry in of 1 • Depending on final result use a multiplexer to choose correct result ECE C 03 Lecture 8 25

Carry Select Adder Redundant hardware to make carry calculation go faster C 8 C 4 C 8 4¥ 2: 1 Mux C 8 4 -Bit Adder [7: 4] 0 Adder Low 4 -Bit Adder [7: 4] 1 Adder High 1 0 1 0 S 7 S 6 S 5 1 0 C 4 S 4 C 0 4 -Bit Adder [3: 0] S 3 S 2 S 1 S 0 compute the high order sums in parallel one addition assumes carry in = 0 the other assumes carry in = 1 ECE C 03 Lecture 8 26

Delay Analysis in Carry Select Adders • Consider an 8 bit adder using two 4 bit chunks • Assume each internal 4 -bit adder uses carry lookahead – needs 4 gate delays to compute sums and 3 gate delays to compute the stage carry-out • The 2: 1 multiplexers add 2 more gate delays • Hence 8 -bit sum is valid after 6 gate delays • COMPARED with 7 gate delays in a carry lookahead unit and 16 gate delays of a ripple carry adder • AGAIN ASSUME that all gate delays are equal, not true in practice ECE C 03 Lecture 8 27

Theory of Multiplication Basic Concept multiplicand multiplier 1101 (13) * 1011 (11) product of 2 4 -bit numbers is an 8 -bit number 1101 Partial products 0000 1101 10001111 (143) ECE C 03 Lecture 8 28

Combinational Multiplier Partial Product Accumulation S 7 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 A 2 B 0 A 1 B 0 A 0 B 0 A 3 B 1 A 2 B 1 A 1 B 1 A 0 B 1 A 3 B 2 A 2 B 2 A 1 B 2 A 0 B 2 A 3 B 3 A 2 B 3 A 1 B 3 A 0 B 3 S 6 S 5 S 4 S 3 ECE C 03 Lecture 8 S 2 S 1 S 0 29

Partial Product Accumulation Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates! ECE C 03 Lecture 8 30

Combinational Multiplier Another Representation of the Circuit Building block: full adder + and 4 x 4 array of building blocks ECE C 03 Lecture 8 31

Arithmetic Logic Unit Design Sample ALU Logical and Arithmetic Operations Not all operations appear useful, but "fall out" of internal logic ECE C 03 Lecture 8 32

Arithmetic Logic Unit Design Sample ALU Traditional Design Approach M 0 Truth Table & Espresso 23 product terms! Equivalent to 25 gates . i 6. o 2. ilb m. ob fi. p 23 11110111 1 -0100 1 -1110 1001010111 -10001 010 -01 -11011 011 -11 --1000 0 -1 -00 --0010 0 -0 -10 -0100001 -0 -0001000 -1 -1 --1 -01 --0 -11 --110 --011. e s 1 s 0 ci ai bi co 10 10 10 10 10 01 01 01 1 1 ECE C 03 Lecture 8 S 1 0 S 0 0 0 1 1 0 0 0 1 1 Ci X X X 0 0 0 1 1 1 Ai 0 1 0 1 0 0 1 1 0 1 0 0 1 1 Bi X X X X 0 1 0 1 X X 0 1 0 1 Fi 0 1 1 0 1 0 0 1 0 1 1 0 Ci+1 X X X X 0 0 0 1 1 1 1 1 0 33 1

Sample ALU Arithmetic Logic Unit Design Multilevel Implementation. model alu. espresso. inputs m s 1 s 0 ci ai bi. outputs fi co. names m ci co [30] [33] [35] fi 110 --- 1 -1 -11 - 1 --01 -1 1 --00 -0 1 S 1. names m ci [30] [33] co Bi -1 -1 1 --11 1 M S 1 111 - 1 Bi. names s 0 ai [30] 01 1 S 0 10 1 Ai. names m s 1 bi [33] 111 1. names s 1 bi [35] 0 - 1 -0 1. end [35] [33] Ci [33] [30] [33] Co M Ci [30] M Ci Co Ci [30] [33] Co [30] [35] Co [30] [35] Fi 12 Gates ECE C 03 Lecture 8 34

Sample ALU Arithmetic Logic Unit Design Clever Multi-level Logic Implementation S 1 Bi S 0 Ai M X 1 A 2 Ci S 1 = 0 blocks Bi Happens when operations involve Ai only Same is true for Ci when M = 0 Addition happens when M = 1 X 2 Bi, Ci to Xor gates X 2, X 3 S 0 = 0, X 1 passes A S 0 = 1, X 1 passes A A 3 A 4 O 1 Ci+1 Arithmetic Mode: Or gate inputs are Ai Ci and Bi (Ai xor Ci) X 3 Logic Mode: Fi Cascaded XORs form output from Ai and Bi ECE C 03 Lecture 8 35 8 Gates (but 3 are XOR)

Arithmetic Logic Unit Design 74181 TTL ALU ECE C 03 Lecture 8 36

Arithmetic Logic Unit Design 74181 TTL ALU Note that the sense of the carry in and out are OPPOSITE from the input bits 19 21 23 2 18 20 22 1 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 7 Cn 8 M 181 F 3 F 2 F 1 F 0 13 11 10 9 A=B 14 Cn+4 16 G 17 P 15 6 15 2 4 5 14 1 3 S 2 S 1 S 0 3 4 5 6 182 P 3 P 2 P 1 P 0 G 3 G 2 G 1 G 0 P G 7 10 Cn+z 9 Cn+y 11 Cn+x 12 13 Cn Fortunately, carry lookahead generator maintains the correct sense of the signals ECE C 03 Lecture 8 37

Arithmetic Logic Unit Design 19 A 3 21 A 2 181 F 3 23 A 1 F 2 2 A 0 F 1 18 B 3 F 0 20 B 2 A=B 22 B 1 Cn+4 1 B 0 G 7 Cn P 8 M S 3 S 2 S 1 S 0 3 4 5 6 19 21 23 2 18 20 22 1 7 8 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 Cn M 13 11 10 9 14 16 17 15 F 3 13 F 2 11 F 1 10 F 0 9 A=B 14 Cn+4 16 G 17 P 15 C 16 181 S 3 S 2 S 1 S 0 3 4 5 6 19 A 3 21 A 2 23 A 1 2 A 0 18 B 3 20 B 2 22 B 1 1 B 0 7 Cn 8 M 16 -bit ALU with Carry Lookahead F 3 F 2 F 1 F 0 A=B Cn+4 G P 181 13 11 10 9 14 16 17 15 6 P 3182 15 P 2 2 P 1 P 4 P 0 G 5 G 3 14 G 2 Cn+z 1 G 1 Cn+y 3 G 0 Cn+x 13 Cn 7 10 9 11 12 S 3 S 2 S 1 S 0 3 4 5 6 C 0 19 21 23 2 18 20 22 1 7 8 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 Cn M F 3 F 2 F 1 F 0 A=B Cn+4 G P 181 13 11 10 9 14 16 17 15 S 3 S 2 S 1 S 0 3 4 5 6 ECE C 03 Lecture 8 38

General Logical Function Unit Statement of the Problem: 3 control inputs: C 0, C 1, C 2 2 data inputs: A, B 1 output: F Similar to the main computation unit in a Microprocessor ECE C 03 Lecture 8 39

Logical Function Unit Formulate as a truth table Choose implementation technology 4 TTL packages: 4 x 2 -input NAND 4 x 2 -input NOR 2 x 2 -input XOR 8: 1 MUX A B A B + 5 V DD D D D S 01 2 3 4 5 6 7 0 S E 1 N Q S O 2 8: 1 Mux C 2 C 1 C 0 F ECE C 03 Lecture 8 40

Logical Function Unit Follow implementation procedure C 1 C 2 AB 00 C 0=0 00 1 01 11 10 1 1 01 11 1 10 1 1 5 gates, 5 inverters 1 1 C 2 AB 00 C 0=1 00 1 1 01 1 11 Also four packages: 4 x 3 -input NAND 1 x 4 -input NAND 10 1 01 11 1 F = C 2' A' B' + C 0' A' B + C 1' A B Alternative: PAL/PLA single package 1 10 ECE C 03 Lecture 8 41

Summary • Review of Arithmetic Number Representation • Adders - Ripple carry, Carry Lookahead, Carry Select Adders • Combinational multipliers • Arithmetic and Logic Unit (ALU) • General function circuits • NEXT LECTURE: Memory Elements and Clocking • READING: Katz 6. 1, 6. 2, 6. 3, Dewey 8. 1, 8. 2 ECE C 03 Lecture 8 42