Lecture 5 Combinational Logic Implementation Using Multiplexers ROMS
Lecture 5 Combinational Logic Implementation Using Multiplexers, ROMS, FPGAs Prith Banerjee ECE C 03 Advanced Digital Logic Design Spring 1998 ECE C 03 Lecture 5 1
Outline • • • Combinational Logic Implementations Multiplexers Decoders ROMS Field Programmable Logic Arrays READING: Katz 4. 2. 2, 4. 2. 3, 4. 2. 4, 4. 2. 5, 10. 3, Dewey 5. 7 ECE C 03 Lecture 5 2
Use of Multiplexers/Selectors Multi-point connections A 0 Sa A 1 B 0 B 1 MUX A B Multiple input sources Sb Sum Ss Multiple output destinations DEMUX S 0 S 1 ECE C 03 Lecture 5 3
General Concept of Using Multiplexers 2 n data inputs, n control inputs, 1 output n used to connect 2 points to a single point control signal pattern form binary index of input connected to output Z = A' I 0 + A I 1 A 0 1 Functional form Logical form ECE C 03 Lecture 5 Z I 0 I 1 0 0 1 1 I 0 0 0 1 1 A 0 1 0 1 Z 0 0 1 1 1 Two alternative forms for a 2: 1 Mux Truth Table 4
Use of Multiplexers/Selectors 2: 1 I 0 Z = A' I 0 + A I 1 Z mux I 1 A I 0 I 1 I 2 I 3 4: 1 mux A I 0 I 1 I 2 I 3 Z B 8: 1 mux I 4 I 5 I 6 I 7 A Z = A' B' I 0 + A' B I 1 + A B' I 2 + A B I 3 B Z C Z = A' B' C' I 0 + A' B' C I 1 + A' B C' I 2 + A' B C I 3 + A B' C' I 4 + A B' C I 5 + A B C' I 6 + A B C I 7 n -1 2 In general, Z = S m I k=0 k k in minterm shorthand form for a 2 n : 1 Mux ECE C 03 Lecture 5 5
Alternative Implementation A B I 0 Z I 1 I 2 I 3 Transmission Gate Implementation of 4: 1 Mux Gate Level Implementation of 4: 1 Mux twenty transistors thirty six transistors ECE C 03 Lecture 5 6
Design of Large Multiplexers Large multiplexers can be implemented by cascaded smaller ones I 0 I 1 I 2 I 3 0 4: 1 1 mux 2 3 S S I 4 I 5 I 6 I 7 0 4: 1 1 mux 2 3 S 1 S 0 1 B Control signals B and C simultaneously choose one of I 0 -I 3 and I 4 -I 7 8: 1 mux 0 2: 1 mux 1 S 0 Z Control signal A chooses which of the upper or lower MUX's output to gate to Z I 0 0 I 1 1 S C C A I 2 0 I 3 1 S 0 1 Alternative 8: 1 Mux Implementation C I 4 0 I 5 1 S C I 6 0 I 7 1 S ECE C 03 Lecture 5 Z 2 3 S 0 S 1 A B 7 C
2 Multiplexers/Selectors as General Purpose Blocks n-1 : 1 multiplexer can implement any function of n variables n-1 control variables; remaining variable is a data input to the mux Example: F(A, B, C) = m 0 + m 2 + m 6 + m 7 = A' B' C' + A' B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1) 1 0 0 0 1 1 0 1 2 3 4 5 6 7 F 8: 1 MUX S 2 S 1 S 0 A B C A 0 0 1 1 B 0 0 1 1 C 0 1 0 1 F 1 0 0 0 1 1 C C 0 1 0 1 2 3 4: 1 MUX S 1 A F S 0 B 1 "Lookup Table" ECE C 03 Lecture 5 8
Generalization of Multiplexer/Selector Logic F I I … I 1 n-1 Mux control variables single Mux data variable … 2 n 0 1 0 0 0 1 1 Four possible configurations of the truth table rows 0 In In 1 Can be expressed as a function of In, 0, 1 Example: G(A, B, C, D) can be implemented by an 8: 1 MUX: K-map Choose A, B, C as control variables Multiplexer Implementation TTL package efficient May be gate inefficient ECE C 03 Lecture 5 1 D 0 1 D D 0 1 2 3 4 5 6 7 G 8: 1 mux S 2 A S 1 B S 0 C 9
Decoders/Demultiplexers Decoder: single data input, n control inputs, 2 n outputs control inputs (called select S) represent Binary index of output to which the input is connected data input usually called "enable" (G) 1: 2 Decoder: O 0 = G • S; O 1 = G • S 3: 8 Decoder: O 0 = G • S 0 • S 1 • S 2 O 1 = G • S 0 • S 1 • S 2 2: 4 Decoder: O 0 = G • S 0 • S 1 O 2 = G • S 0 • S 1 • S 2 O 1 = G • S 0 • S 1 O 3 = G • S 0 • S 1 • S 2 O 2 = G • S 0 • S 1 O 4 = G • S 0 • S 1 • S 2 O 3 = G • S 0 • S 1 O 5 = G • S 0 • S 1 • S 2 O 6 = G • S 0 • S 1 • S 2 ECE C 03 Lecture 5 O 7 = G • S 0 • S 1 • S 2 10
Alternative Implementations G Output 0 Select /G Select Output 0 Output 1 1: 2 Decoder, Active Low Enable 1: 2 Decoder, Active High Enable /G G Select 0 Output 1 Output 2 Output 3 Select 0 Select 1 2: 4 Decoder, Active High Enable Select 1 2: 4 Decoder, Active Low Enable ECE C 03 Lecture 5 11
Switch Level Implementations Select G G Output 0 Select "0" Select Output 1 Select Naive, Incorrect Implementation Select All outputs not driven at all times "0" Select Correct 1: 2 Decoder Implementation ECE C 03 Lecture 5 12
Switch Implementation of 2: 4 Decoder Select G 0 Select 1 Output 0 Operation of 2: 4 Decoder "0" S 0 = 0, S 1 = 0 "0" G Output 1 "0" three diagonal paths "0" G one straight thru path Output 2 "0" G Output 3 "0" ECE C 03 Lecture 5 13
Decoder as a Logic Building Block Enb 3: 8 dec S 2 A S 1 B S 0 0 1 2 3 4 5 6 7 ABC ABC Decoder Generates Appropriate Minterm based on Control Signals C Example Function: F 1 = A' B C' D + A' B' C D + A B C D F 2 = A B C' D' + A B C F 3 = (A' + B' + C' + D') ECE C 03 Lecture 5 14
Decoder as a Logic Building Block Enb 4: 16 dec S 3 S 2 S 1 S 0 A B C D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ABCD ABCD ABCD ABCD F 1 F 2 F 3 If active low enable, then use NAND gates! ECE C 03 Lecture 5 15
Alternative Implementation of 32: 1 Mux I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 C D E EN I 31 7 151 EN 1 6 5 1 Y 5 I 23 7 151 41 4 6 3 W 6 EN 1 5 52 2 1 3 5 1 I 15 7 151 41 4 40 Y 6 1 52 3 W EN 1 6 5 2 3 3 1 Y 19 1 5 C 7 151 41 4 B 4 0 W 1 6 A 6 5 3 0 22 5 9 1 3 1 Y 15 C 4 4 0 1 6 B 13 W 0 A 2 9 1 1 1 C B 0 1 A S 2 0 1 S 0 1 GA 3 4 A 2 5 A 1 6 A 0 13 12 11 10 1 5 1 1 G 1 Y 3 1391 Y 2 A 3 1 B 1 Y 1 2 1 A 1 Y 0 B 15 2 G 2 Y 3 2 Y 2 13 2 B 2 Y 1 14 2 A 2 Y 0 153 YA 7 F(A, B, C, D, E) B 3 B 2 YB 9 B 1 B 0 GBS 1 SO 2 14 A B 7 6 5 4 9 10 11 12 7 EN 146 5 154 I 31 7 151 1 3 6 7 EN 22 I 5 145 31 Y 5 154 I 23 7 I 4151 40 3 7 EN 146 I 3 1 W 6 2 I 5 5 I 2 2 9 C 154 I 1 3 1 Y 10 5 B I 15 7 I 4151 3 I 0 4 0 W 116 A 7 EN 146 I 3 1 I 5 5 I 2 22 C 9 C S 2 154 I 1 31 Y 10 5 B I 7 7 I 4 151 S 1 I 6 6 I 3 1 3 I 0 40 WD 116 A I 5 5 I 2 2 2 C 9 C S 2 E S 0 5 I 4 4 I 1 3 1 Y 10 S 1 D 11 B I 3 3 I 0 4 0 W 6 A I 2 2 C 9 S 2 S 0 E C I 1 1 10 B S 1 D I 0 0 11 A C S 2 E S 0 D S 1 E S 0 F(A, B, C, D, E) Multiplexer + Decoder Multiplexer Only ECE C 03 Lecture 5 16
5: 32 Decoder EN S 4 S 3 1 G 1 Y 3 139 1 Y 2 1 B 1 Y 1 1 A 1 Y 0 2 G 2 Y 3 2 Y 2 2 B 2 Y 1 2 A 2 Y 0 EN S 2 S 1 S 0 Y 31 5: 32 Decoder Subsystem . . . S 2 S 1 S 0 Y 0 S 4 S 3 S 2 S 1 S 0 ECE C 03 Lecture 5 G 1 G 2 A G 2 B Y 7 Y 6 Y 5 Y 4 138 Y 3 Y 2 C Y 1 B Y 0 A Y 31 Y 30 Y 29 Y 28 Y 27 Y 26 Y 25 Y 24 Y 7 G 1 G 2 A Y 6 G 2 B Y 5 138 Y 4 Y 3 Y 2 C Y 1 B Y 0 A Y 23 Y 22 Y 21 Y 20 Y 19 Y 18 Y 17 Y 16 Y 7 G 1 G 2 A Y 6 G 2 B Y 5 138 Y 4 Y 3 C Y 2 B Y 1 A Y 0 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y 9 Y 8 G 1 Y 7 G 2 A Y 6 G 2 B Y 5 138 Y 4 Y 3 Y 2 C Y 1 B Y 0 A Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 17
Read-Only Memories ROM: Two dimensional array of 1's and 0's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize Address is input, selected word is output +5 V +5 V n 2 -1 Dec i Word Line 0011 j Word Line 1010 0 0 n-1 Address Bit Lines C 03 Lecture 5 Internal ECE Organization 18
Implementing Logic with ROMs F 0 = A' B' C + A B' C' + A B' C F 1 = A' B' C + A' B C' + A B C F 2 = A' B' C' + A' B' C + A B' C' F 3 = A' B C + A B' C' + A B C' A 0 0 1 1 Address ROM 8 w ords ¥by 4 bits A B C address F 0 F 1 F 2 outputs B 0 0 1 1 C 0 1 0 1 F 0 0 1 1 0 0 F 1 0 1 1 0 0 1 F 2 1 1 0 0 0 F 3 0 0 0 1 1 0 Word Contents F 3 ECE C 03 Lecture 5 19
ROMs vs PLAs Memory array Not unlike a PLA structure with a fully decoded AND array! Decoder 2 n word lines n address lines 2 n words by m bits m output lines ROM vs. PLA: ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e. g. , code converters) (3) little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions ECE C 03 Lecture PAL problem: constrained fan-ins on OR 5 planes 20
2764 EPROM 8 K x 8 2764 VPP PGM A 12 A 11 A 10 O 7 A 9 O 6 A 8 O 5 A 7 O 4 A 6 O 3 A 5 O 2 A 4 O 1 A 3 O 0 A 2 A 1 A 0 CS OE Read-Only Memories 2764 VPP PGM A 12 A 11 A 10 O 7 A 9 O 6 A 8 O 5 A 7 O 4 A 6 O 3 A 5 O 2 A 4 O 1 A 3 O 0 A 2 A 1 A 0 CS U 3 OE + A 13 /OE A 12: A 0 D 15: D 8 D 7: D 0 + 2764 VPP PGM A 12 A 11 A 10 O 7 A 9 O 6 A 8 O 5 A 7 O 4 A 6 O 3 A 5 O 2 A 4 O 1 A 3 O 0 A 2 A 1 A 0 CS U 1 OE 2764 VPP PGM A 12 A 11 A 10 O 7 A 9 O 6 A 8 O 5 A 7 O 4 A 6 O 3 A 5 O 2 A 4 O 1 A 3 O 0 A 2 A 1 A 0 CS U 2 OE + + 2764 VPP PGM A 12 A 11 A 10 O 7 A 9 O 6 A 8 O 5 A 7 O 4 A 6 O 3 A 5 O 2 A 4 O 1 A 3 O 0 A 2 A 1 A 0 CS U 0 OE 16 K x 16 Subsystem ECE C 03 Lecture 5 21
Combinational Design with FPGAs Programmable Logic Devices = PLD PALs, PLAs = 10 - 100 Gate Equivalents Field Programmable Gate Arrays = FPGAs • Altera MAX Family • Actel Programmable Gate Array • Xilinx Logical Cell Array 100 - 1000(s) of Gate Equivalents! ECE C 03 Lecture 5 22
Altera Erasable Programmable Logic Devices Historical Perspective: PALs – same technology as programmed once bipolar PROM EPLDs — CMOS erasable programmable ROM (EPROM) erased by UV light Altera building block = MACROCELL CLK 8 Product Term AND-OR Array + Programmable MUX's Clk MUX AND ARRAY Output MUX Q pad I/O Pin Invert Control F/B MUX Programmable polarity ECE C 03 Lecture 5 Seq. Logic Block Programmable feedback 23
Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Global CLK 1 Clk MUX Synchronous Mode Flipflop controlled by global clock signal OE/Local CLK Q EPROM Cell Global CLK 1 Clk MUX local signal computes output enable Asynchronous Mode OE/Local CLK Q Flipflop controlled by locally generated clock signal EPROM Cell + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear ECE C 03 Lecture 5 function 24
Altera EPLDs AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Altera solution: Multiple Array Matrix (MAX) Logic Array Blocks (similar to macrocells) LAB A LAB H LAB B LAB C LAB G P I A LAB D LAB F Global Routing: Programmable Interconnect Array EPM 5128: 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB E ECE C 03 Lecture 5 25
Altera EPLDs LAB Architecture I/O Pad Macrocell ARRAY I N P U T S I/O Block I/O Pad P I A Expander Product Term ARRAY Macrocell P-Terms Expander Terms shared among all macrocells within the LAB ECE C 03 Lecture 5 26
Altera EPLDs P 22 V 10 PAL INCREMENT 2904 1 0 0 FIRST FUSE NUMBERS 44 88 132 176 220 264 308 352 396 4 8 12 16 20 24 28 32 36 40 2948 2992 3036 3080 3124 3168 3212 3256 3300 3344 3388 3432 3476 3520 3564 3608 ASYNCHRONOUS RESET (TO ALL REGISTERS) 11 D AR 10 Q 01 SP 23 5808 P R 1 0 5809 OUTPUT LOGIC MACROCELL 3696 3740 3784 3828 3872 3916 3960 4004 4048 4092 4136 4180 4224 4268 22 P - 5810 R - 5811 924 17 P - 5820 R - 5821 4312 OUTPUT LOGIC MACROCELL 4356 4400 4444 4488 4532 4576 4620 4664 4708 4752 4796 4840 21 P - 5812 R - 5813 1496 OUTPUT LOGIC MACROCEL L 16 P - 5822 R - 5823 8 4884 OUTPUT LOGIC MACROCELL 4928 4972 5016 5060 5104 5148 5192 5236 5280 5324 20 P - 5814 R - 5815 4 OUTPUT LOGIC MACROCEL L 15 P - 5824 R - 5825 9 5368 2156 2200 2244 2288 2332 2376 2420 2464 2508 2552 2596 2640 2684 2728 2772 2816 2860 5 OUTPUT LOGIC MACROCEL L 7 3 1540 1584 1628 1672 1716 1760 1804 1848 1892 1936 1980 2024 2068 2112 P - 5818 R - 5819 3652 2 968 1012 1056 1100 1144 1188 1232 1276 1320 1364 1408 1452 18 6 440 484 528 572 616 660 704 748 792 836 880 OUTPUT LOGIC MACROCEL L OUTPUT LOGIC MACROCELL 5412 5456 5500 5544 5588 5632 5676 5720 OUTPUT LOGIC MACROCEL L 14 P - 5826 R - 5827 19 10 P - 5816 R - 5817 SYNCHRONOUS PRESET (TO ALL REGISTERS) 5764 11 INCREMEN T 13 0 4 8 12 16 20 24 28 32 36 40 Supports large number of product terms per output Latches and muxes associated with output pins ECE C 03 Lecture 5 27
+ rows of interconnect Anti-fuse Technology: Program Once Use Anti-fuses to build up long wiring runs from short segments I/O Buffers, Programming and Test Logic Module I/O Buffers, Programming and Test Logic Rows of programmable logic building blocks I/O Buffers, Programming and Test Logic Actel Programmable Gate Arrays Wiring Tracks 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled 28 gates ECE C 03 Lecture 5
Actel Logic Module SOA S 0 Basic Module is a Modified 4: 1 Multiplexer S 1 D 0 2: 1 MUX D 1 2: 1 MUX Y D 2 2: 1 MUX D 3 R SOB Example: Implementation of S-R Latch "0" 2: 1 MUX Q "1" 2: 1 MUX ECE C 03 Lecture 5 S 29
Actel Interconnect Logic Module Horizontal Track Anti-fuse Vertical Track Interconnection Fabric ECE C 03 Lecture 5 30
Actel Routing Example Logic Module Input Logic Module Output Input Jogs cross an anti-fuse minimize the # of jobs for speed critical circuits 2 - 3 hops for most interconnections ECE C 03 Lecture 5 31
Xilinx Logic Cell Arrays CMOS Static RAM Technology: programmable on the fly! All personality elements connected into serial shift register Shift in string of 1's and 0's on power up IOB CLB IOB Wiring Channels CLB IOB General Chip Architecture: • Logic Blocks (CLBs) • IO Blocks (IOBs) • Wiring Channels IOB IOB ECE C 03 Lecture 5 CLB 32
Xilinx LCA Architecture Inputs: Tri-state enable bit to output input, output clocks Outputs: input bit Internal FFs for input & output paths Program Controlled Options OUT INV TS INV OUTPUT SOURCE Pull-up used with unused IOBs PASSIVE PULLUP Vcc Enable Output PAD MUX Out D Q Output Buffer R Direct In Fast/Slow outputs 5 ns vs. 30 ns rise SLEW RATE Q Registered In D TTL or CMOS Input Buffer R Clocks ECE C 03 Lecture 5 Global Reset 33
Xilinx LCA Architecture Configurable Logic Block: CLB 2 FFs Reset DIN Any function of 5 Variables Global Reset A B C D E Clock, Clock Enb Q 1 D RD Q CE F Mux X Mux Y Combinational Function Generator Q 2 G Mux Clock Independent DIN Mux D RD Q CE Clock Enable ECE C 03 Lecture 5 34
Xilinx CLB Function Generator A B Q 1 A B Mux C Mux D E Q 2 Q 1 C D E F Function of 5 Variables Mux Function of 4 Variables F Function of 4 Variables G Mux Q 2 G Q 1 A B Any function of 5 variables C D E Mux Mux Q 2 ECE C 03 Lecture 5 Two Independent Functions of 4 variables each 35
Xilinx CLB Function Generator Q 1 A B Mux C Mux Function of 4 Variables D Certain Limited Functions of 6 Variables E F Q 2 Mux Q 1 G A B Mux C Mux Function of 4 Variables D Q 2 ECE C 03 Lecture 5 36
Xilinx Application Examples 5 -Input Parity Generator Implemented with 1 CLB: F = A xor B xor C xor D xor E (this is a different parity generator than the one in Chapter 8!) 2 -bit Comparator: A B = C D or A B > C D Implemented with 1 CLB: (GT) F = A C + A B D + B C D (EQ) G = A B C D + A B C D ECE C 03 Lecture 5 37
Xilinx Application Examples n-Input Majority Circuit Assert 1 whenever n/2 or greater inputs are 1 5 -input Majority Circuit 9 Input Parity Logic CLB 7 -input Majority Circuit CLB CLB n-input Parity Functions 5 input = 1 CLB, 2 Levels of. Lecture CLBs 5 yield up to 25 inputs! ECE C 03 38
Xilinx Application Examples 4 -bit Binary Adder A 3 B 3 A 2 B 2 CLB Cout A 1 B 1 CLB S 3 CLB S 2 C 2 A 3 B 3 A 2 B 2 CLB A 0 B 0 Cin C 1 CLB S 1 C 0 S 0 A 1 B 1 A 0 B 0 Cin S 2 CLB S 0 S 3 Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out S 1 C 2 ECE C 03 Lecture 5 39
Xilinx Interconnect Architecture Interconnect Direct Connections Global Long Line DI CE A B X C CLB 0 K Y E D R Horizontal Long Line Switching Matrix Horizontal/Vertical Long Lines Switching Matrix Connections DI CE A B X C CLB 1 K Y E D R Horizontal Long Line DI CE A B X C CLB 3 K Y E D R DI CE A B X C CLB 2 K Y E D R Vertical Long Lines ECE C 03 Lecture 5 Global Long Line 40
Comparison of Recent Xilinx Architectures ECE C 03 Lecture 5 41
Summary • • • Combinational Logic Implementations Multiplexers Decoders ROMS Field Programmable Logic Arrays READING: Katz 4. 2. 2, 4. 2. 3, 4. 2. 4, 4. 2. 5, 10. 3, Dewey 5. 7 ECE C 03 Lecture 5 42
- Slides: 42