Lecture 4part 1 Topics covered Arithmetic Number representation

Lecture 4(part 1) Topics covered: Arithmetic

Number representation Integers are represented as binary vectors Suppose each word consists of 32 bits, labeled 0… 31. 31 30. . . . MSB (most significant bit) 1 0 LSB (least) Value of the binary vector interpreted as unsigned integer is: V(b) = b 31. 231 + b 30. 230 + b 29. 229 +. . + b 1. 21 + b 0. 20 More generally in N bits, 1

Number representation (contd. . ) q We need to represent both positive and negative integers. q Three schemes are available for representing both positive and negative integers: Sign and magnitude. u 1’s complement. u 2’s complement. u q All schemes use the Most Significant Bit (MSB) to carry the sign information: If MSB = 0, bit vector represents a positive integer. u If MSB = 1, bit vector represents a negative integer. u 2

Number representation (contd. . ) q Sign and Magnitude: Lower N-1 bits represent the magnitude of the integer u MSB is set to 0 or 1 to indicate positive or negative u q 1’s complement: Construct the corresponding positive integer (MSB = 0) u Bitwise complement this integer u q 2’s complement: Construct the 1’s complement negative integer u Add 1 to this u 3

Number representation (contd. . ) B Values represented b 3 b 2 b 1 b 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 Sign and magnitude 1's complement +7 +6 +5 +4 +3 +2 +1 +0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 +7 +6 +5 +4 +3 +2 +1 +0 -7 -6 -5 -4 -3 -2 - 1 -0 2's complement + + + + - 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 4

Number representation (contd. . ) Range of numbers that can be represented in N bits Unsigned: Sign and magnitude: One’s complement: : 0 has both positive and negative representation Two’s complement: : 0 has a single representation, easier to add/subtract. 5

Value of a bit string in 2’s complement How to determine the value of an integer given: Integer occupies N bits. 2’s complement system is in effect. Binary vector b represents a negative integer, what is V(b). Write b = 1 bn-2 bn-3. . . . b 1 b 0 Then V(b) = -2 n-1 + bn-2 2 n-2 + bn-3 2 n-3 +. . + b 2 22 + b 1 21 + b 0 20 (v(b) = -2 n-1 + bn-2 2 n-2 + bn-3 2 n-3 +. . + b 2 22 + b 1 21 + b 0 20 showing negative and positive parts of the expression ) So, in 4 bits, 1011 is v(1011) = -8 + 3 = -5 6

Addition of positive numbers Add two one-bit numbers 0 + 0 0 1 + 0 1 0 + 1 1 1 + 1 10 Carry-out To add multiple bit numbers: • Add bit pairs starting from the low-order or LSB (right end of bit vector) • Propagate carries towards the high-order or MSB (left end of bit vector) 7

Addition and subtraction of signed numbers q We need to add and subtract both positive and negative numbers. q Recall the three schemes of number representation. q Sign-and-magnitude scheme is the simplest representation, but it is the most awkward (inapplicable)for addition and subtraction operations. (has two forms for the zero number) q 2’s complement is the most efficient method for performing addition and subtraction of signed numbers. 8

Rules for addition and subtraction of signed numbers in 2’s complement form q To add two numbers: Add their n-bit representations. u Ignore the carry out from MSB position. u Sum is the algebraically correct value in the 2’s complement representation as long as the answer is in the range – 2 n-1 through +2 n-1 – 1. u q To subtract two numbers X and Y (X-Y): Form the 2’s complement of Y. u Add it to X using Rule 1. u Result is correct as long as the answer lies in the range – 2 n-1 through +2 n-1 – 1. u 9

Addition Operations using Two’s complement The main advantage of using two’s complement is converting subtraction into addition Note: Don’t forget to neglect the carry bit 10

Subtraction Operations using Two’s complement 11

Overflow in integer arithemtic q When the result of an arithmetic operation is outside the representable range an arithmetic overflow has occurred. u Range is – 2 n-1 through +2 n-1 – 1 for n-bit vector. q When adding unsigned numbers, carry-out from the MSB position serves as the overflow indicator. q When adding signed numbers, this does not work. q Using 4 -bit signed numbers, add +7 and +4: u Result is 1011, which represents – 5. q Using 4 -bit signed integers, add – 4 and – 6: u Result is 0110, which represents +6. 0111(+7) + 0100(+4) ------1011(-5) Overflow 1100(-4) + 1010(-6) ------0110(+6) Overflow 12

Overflow in integer arithmetic (contd. . ) q Overflow occurs when both the numbers have the same sign. u Addition of numbers with different signs cannot cause an overflow. q Carry-out signal from the MSB (sign-bit) position is not a sufficient indicator of overflow when adding signed numbers. q Detect overflow when adding X and Y: Examine the signs of X and Y. u Examine the signs of the result S. u When X and Y have the same sign, and the sign of the result differs from the signs of X and Y, overflow has occurred. u How to detect overflow by a logical circuit? u Overflow =? ? ? ? ? 13

Addition/subtraction of signed numbers xi yi Carry-in ci Sumsi Carry-outci +1 0 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 At the ith stage: Input: ci is the carry-in Output: si is the sum ci+1 carry-out to (i+1)st state si = xi yi ci + xi yi ci = x i Å yi Å ci ci +1 = yi ci + xi yi Example: X 7 +Y = +6 Z 13 0 = + 00 1 1 1 1 0 0 1 0 Carry-out ci+1 xi yi si Carry-in ci Legend for stage i 14

Addition logic for a single stage Sum Carry yi c i xi yi xi c si ci i xi ci + 1 yi Full adder (FA) c i +1 x i yi ci s i Full Adder (FA): Symbol for the complete circuit for a single stage of addition. 15

n-bit subtractor • Recall X – Y is equivalent to adding 2’s complement of Y to X. • 2’s complement is equivalent to 1’s complement + 1. • X – Y = X + Y + 1 • 2’s complement of positive and negative numbers is computed similarly. x y n- 1 x n- 1 y 1 c c n x 1 c n- 1 y 0 0 1 FA FA FA s s s n- 1 Most significant bit (MSB) position 1 1 0 Least significant bit (LSB) position 16

n-bit adder/subtractor xn - yn - 1 1 cn cn - FA sn - x 1 1 y 1 x 0 c 1 FA s 0 Most significant bit (MSB) position xn - cn Least significant bit (LSB) position yn - 1 1 sn - x 1 cn - FA 1 Most significant bit (MSB) position c 0 FA s 1 1 Adder inputs: xi, yi, co=0 y 0 1 y 1 FA s 1 x 0 c 1 Subtractor inputs: xi, yi, co=1 y 0 FA 1 s 0 Least significant bit (LSB) position 17

n-bit adder/subtractor (contd. . ) y y n- 1 1 y 0 Add/Sub control x c n- 1 x x 1 0 n-bit adder n c 0 s n- 1 s 0 • Add/sub control = 0, addition. • Add/sub control = 1, subtraction. 18

Detecting overflows q Overflows can only occur when the sign of the two operands is the same. q Overflow occurs if the sign of the result is different from the sign of the operands. q Recall that the MSB represents the sign. u xn-1, yn-1, sn-1 represent the sign of operand x, operand y and result s respectively. q Circuit to detect overflow can be implemented by the following logic expressions: 19

n-bit adder • Cascade n full adder (FA) blocks to form a n-bit adder. • Carries propagate or ripple through this cascade, n-bit ripple carry adder. x y n- 1 x n- 1 c c n y 1 x 1 c n- 1 y 0 1 FA FA FA s s s n- 1 Most significant bit (MSB) position 1 0 c 0 0 Least significant bit (LSB) position Carry-in c 0 into the LSB position provides a convenient way to perform subtraction. 20

kn-bit adder K n-bit numbers can be added by cascading k n-bit adders. xkn - 1 ykn - 1 x 2 n - 1 y 2 n - n-bit adder c kn s kn - 1 1 xn y n k - 1) n s 2 n - 1 y 1 n- 1 cn n-bit adder s( xn - s n x 0 y 0 n-bit adder s n- 1 c 0 s 0 Each n-bit adder forms a block, so this is cascading of blocks. Carries ripple or propagate through blocks, Blocked Ripple Carry Adder 21

Computing the add time y 0 x 0 c 1 FA c 0 Consider 0 th stage: • c 1 is available after 2 gate delays. • s 1 is available after 1 gate delay. s 0 Carry Sum yi c i xi yi ci si xi c i +1 x i yi 22

Computing the add time (contd. . ) Cascade of 4 Full Adders, or a 4 -bit adder y 3 x 3 c 4 FA s 3 y 2 x 2 c 3 FA s 2 y 1 x 1 c 2 FA s 1 x 0 c 1 y 0 FA c 0 s 0 • s 0 available after 1 gate delays, c 1 available after 2 gate delays. • s 1 available after 3 gate delays, c 2 available after 4 gate delays. • s 2 available after 5 gate delays, c 3 available after 6 gate delays. • s 3 available after 7 gate delays, c 4 available after 8 gate delays. For an n-bit adder, sn-1 is available after 2 n-1 gate delays cn is available after 2 n gate delays. 23

Fast addition Recall the equations: Second equation can be written as: We can write: • Gi is called generate function and Pi is called propagate function • Gi and Pi are computed only from xi and yi and not ci, thus they can be computed in one gate delay after X and Y are applied to the inputs of an n-bit adder. 24

Carry lookahead • All carries can be obtained 3 gate delays after X, Y and c 0 are applied. -One gate delay for Pi and Gi -Two gate delays in the AND-OR circuit for ci+1 • All sums can be obtained 1 gate delay after the carries are computed. • Independent of n, n-bit addition requires only 4 gate delays. • This is called Carry Lookahead adder. 25

Carry-lookahead adder x 3 y 3 c 4 B cell x 2 y 2 c 3 B cell s 3 G 3 P 3 x 1 y 1 c 2 B cell s 2 G 2 x 0 y 0 c 1 B cell s 1 P 2 G 1 . c 0 4 -bit carry-lookahead adder. s 0 P 1 G 0 P 0 Carry-lookahead logic xi yi . . B-cell for a single stage. . ci B cell Gi Pi si 26

Carry lookahead adder (contd. . ) q Performing n-bit addition in 4 gate delays independent of n is good only theoretically because of fan-in constraints. ci+1 = Gi + Pi. Gi -1 + Pi Pi-1 Gi -2 +. . + Pi Pi -1. . P 1 G 0 + Pi Pi -1. . . P 0 c 0 q Last AND gate and OR gate require a fan-in of (n+1) for a nbit adder. u For a 4 -bit adder (n=4) fan-in of 5 is required. u Practical limit for most gates. q In order to add operands longer than 4 bits, we can cascade 4 -bit Carry-Lookahead adders. Cascade of Carry-Lookahead adders is called Blocked Carry-Lookahead adder. 27

Blocked Carry-Lookahead adder Carry-out from a 4 -bit block can be given as: Rewrite this as: Subscript I denotes the blocked carry lookahead and identifies the block. Cascade 4 4 -bit adders, c 16 can be expressed as: 28

Blocked Carry-Lookahead adder (contd. . ) x 15 -12 c 16 y 15 -12 4 -bit adder x 11 -8 c 12 4 -bit adder s 15 -12 G 3 I P 3 I y 11 -8 x 7 -4 c 8 y 7 -4 4 -bit adder s 11 -8 G 2 I P 2 I x 3 -0 c 4 4 -bit adder s 7 -4 G 1 I P 1 I y 3 -0 . c 0 s 3 -0 G 0 I P 0 I Carry-lookahead logic After xi, yi and c 0 are applied as inputs: - Gi and Pi for each stage are available after 1 gate delay. - PI is available after 2 and GI after 3 gate delays. - All carries are available after 5 gate delays. - c 16 is available after 5 gate delays. - s 15 which depends on c 12 is available after 8 (5+3)gate delays (Recall that for a 4 -bit carry lookahead adder, the last sum bit is available 3 gate delays after all inputs are available) 29

Multiplication of unsigned numbers ´ x 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 1 (13) Multiplicand M (11) Multiplier Q Partial product (PP) #1 Partial product (PP) #2 Partial product (PP) #3 Partial product (PP) #4 (143) Product P • Product of 2 n-bit numbers is at most a 2 n-bit number. • We should expect to store a double-length result. Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand. 30

Multiplication of unsigned numbers (contd. . ) q We added the partial products at end. u Alternative would be to add the partial products at each stage. q Rules to implement multiplication are: If the ith bit of the multiplier is 1, shift the multiplicand add the shifted multiplicand to the current value of the partial product. u Hand over the partial product to the next stage u Value of the partial product at the start stage is 0. u 31

Multiplication of unsigned numbers (contd. . ) Typical multiplication cell Bit of incoming partial product (PPi) ith multiplier bit carry out jth multiplicand bit FA carry in Bit of outgoing partial product (PP(i+1)) 32

Combinatorial array multiplier Multiplicand (PP 0) 0 m 3 0 m 2 0 m 1 0 q 0 0 q 2 0 PP 3 q 3 0 p 6 p 5 p 4 p 3 p 1 M PP 2 p 0 ul tip lie q 1 0 r PP 1 p 7 m 0 p 2 , Product is: p 7, p 6, . . p 0 Multiplicand is shifted by displacing it through an array of adders. 33

Combinatorial array multiplier (contd. . ) q Combinatorial array multipliers are: Extremely inefficient. u Have a high gate count for multiplying numbers of practical size such as 32 -bit or 64 -bit numbers. u Perform only one function, namely, unsigned integer product. u q Improve gate efficiency by using a mixture of combinatorial array techniques and sequential techniques requiring less combinational logic. 34

Sequential multiplication q Recall the rule for generating partial products: If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand to the current partial product. u Multiplicand has been shifted left when added to the partial product. u q However, adding a left-shifted multiplicand to an unshifted partial product is equivalent to adding an unshifted multiplicand to a right-shifted partial product. 35

Sequential multiplication (contd. . ) Register A (initially 0) Shift right an - 1 C a 0 qn - 1 q 0 Multiplier Q Add/Noadd control n-bit adder Control sequencer MUX 0 0 mn - 1 m 0 Multiplicand M • Load Register A with 0. • Registers are used to store multiplier and multiplicand. • Each cycle repeat the following: steps: 1. If the LSB q 0=1: -Add the multiplicand to A. -Store carry-out in flip-flop C Else if q 0 = 0 -Do not add. 2. Shift the contents of register A and Q to the right, and discard q 0. 36

Sequential multiplication (contd. . ) Register A (initially 0) Shift right an - 1 C a 0 qn - 1 q 0 Multiplier Q Add/Noadd control Control sequencer n-bit adder MUX M 1 1 0 0 mn - 1 m 0 Multiplicand M Initial configuration 0 C 0 0 A 1 0 1 1 Q 0 0 1 1 0 1 Add Shift First cycle 1 0 0 0 1 1 1 0 Add Shift Second cycle 0 0 1 0 1 0 0 1 1 1 1 No add Shift Third cycle 1 0 0 1 1 0 0 0 1 1 1 1 Add Shift Fourth cycle Product 37