Lecture 35 OUTLINE The MOS Capacitor Final comments
- Slides: 13
Lecture #35 OUTLINE The MOS Capacitor: Final comments The MOSFET: • Structure and operation Reading: Chapter 17. 1 1 Spring 2007 EE 130 Lecture 35, Slide 1
Bias-Temperature Stress Measurement Used to determine mobile charge density in MOS dielectric (units: C/cm 2) Na+ located at lower Si. O 2 interface reduces VFB DVFB Na+ located at upper Si. O 2 interface no effect on VFB Positive oxide charge shifts the flatband voltage in the negative direction: 2 Spring 2007 EE 130 Lecture 35, Slide 2
Clarification: Effect of Interface Traps (c) (b) (a) “Donor-like” traps are charge-neutral when filled, positively charged when empty Positive oxide charge causes C-V curve to shift toward left (more shift as VG decreases) Traps cause “sloppy” C-V and also greatly degrade mobility in channel (a) (b) (c) 3 Spring 2007 EE 130 Lecture 35, Slide 3
Invention of the Field-Effect Transistor In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955. 4 Spring 2007 EE 130 Lecture 35, Slide 4
Modern Field Effect Transistor (FET) • An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying electrode), to modulate the conductance of the semiconductor ® Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode 5 Spring 2007 EE 130 Lecture 35, Slide 5
The Bulk-Si MOSFET GATE LENGTH, Lg OXIDE THICKNESS, Tox Gate Metal-Oxide-Semiconductor Field-Effect Transistor: Desired characteristics: • High ON current • Low OFF current Source Drain Substrate M. Bohr, Intel Developer Forum, September 2004 JUNCTION DEPTH, Xj • “N-channel” & “P-channel” MOSFETs operate in a complementary manner “CMOS” = Complementary MOS CURRENT • Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode VT |GATE VOLTAGE| 6 Spring 2007 EE 130 Lecture 35, Slide 6
N-channel vs. P-channel NMOS PMOS N+ poly-Si P+ poly-Si N+ N+ P+ P-type Si P+ n-type Si • For current to flow, VGS > VT • For current to flow, VGS < VT • Enhancement mode: VT > 0 • Enhancement mode: VT < 0 • Depletion mode: VT > 0 – Transistor is ON when VG=0 V 7 Spring 2007 EE 130 Lecture 35, Slide 7
Enhancement Mode vs. Depletion Mode Enhancement Mode Conduction between source and drain regions is enhanced by applying a gate voltage Depletion Mode A gate voltage must be applied to deplete the channel region in order to turn off the transistor 8 Spring 2007 EE 130 Lecture 35, Slide 8
CMOS Devices and Circuits CIRCUIT SYMBOLS N-channel MOSFET P-channel MOSFET CMOS INVERTER CIRCUIT VDD VOUT S D VIN D GND INVERTER LOGIC SYMBOL VDD VOUT S 0 VDD VIN • When VG = VDD , the NMOSFET is on and the PMOSFET is off. • When VG = 0, the PMOSFET is on and the NMOSFET is off. 9 Spring 2007 EE 130 Lecture 35, Slide 9
“Pull-Down” and “Pull-Up” Devices • In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD. – An NMOSFET functions as a pull-down device when it is turned on (gate voltage = VDD) – A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) VDD Pull-up network PMOSFETs only F(A 1, A 2, …, AN) … A 1 A 2 AN … input signals A 1 A 2 AN Pull-down network NMOSFETs only 10 Spring 2007 EE 130 Lecture 35, Slide 10
CMOS NAND Gate VDD A A B 0 0 0 1 1 B F 1 1 1 0 F A B 11 Spring 2007 EE 130 Lecture 35, Slide 11
CMOS NOR Gate VDD A B 0 0 0 1 1 A F 1 0 0 0 B F A B 12 Spring 2007 EE 130 Lecture 35, Slide 12
CMOS Pass Gate A Y X Y = X if A A 13 Spring 2007 EE 130 Lecture 35, Slide 13
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