Lecture 3 Nonideal Transistor Theory 4 Nonideal Transistor
- Slides: 37
Lecture 3: Nonideal Transistor Theory 4: Nonideal Transistor Theory 1
Outline q Nonideal Transistor Behavior – High Field Effects • Mobility Degradation • Velocity Saturation – Channel Length Modulation – Threshold Voltage Effects • Body Effect • Drain-Induced Barrier Lowering • Short Channel Effect – Leakage • Subthreshold Leakage • Gate Leakage • Junction Leakage q Process and Environmental Variations 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 2
Ideal Transistor I-V q Shockley long-channel transistor models 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 3
Ideal vs. Simulated n. MOS I-V Plot q 65 nm IBM process, VDD = 1. 0 V 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 4
ON and OFF Current q Ion = Ids @ Vgs = Vds = VDD – Saturation q Ioff = Ids @ Vgs = 0, Vds = VDD – Cutoff 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 5
Electric Fields Effects q Vertical electric field: Evert = Vgs / tox – Attracts carriers into channel – Long channel: Qchannel Evert q Lateral electric field: Elat = Vds / L – Accelerates carriers from drain to source – Long channel: v = m. Elat 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 6
Coffee Cart Analogy q Tired student runs from VLSI lab to coffee cart q Freshmen are pouring out of the physics lecture hall q Vds is how long you have been up – Your velocity = fatigue × mobility q Vgs is a wind blowing you against the glass (Si. O 2) wall q At high Vgs, you are buffeted against the wall – Mobility degradation q At high Vds, you scatter off freshmen, fall down, get up – Velocity saturation • Don’t confuse this with the saturation region 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 7
Mobility Degradation q High Evert effectively reduces mobility – Collisions with oxide interface – Essentially carrier mobility depends on Vgs and Vt 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 8
Velocity Saturation q At high Elat, carrier velocity rolls off – Carriers scatter off atoms in silicon lattice – Velocity reaches vsat • Electrons: 107 cm/s • Holes: 8 x 106 cm/s – Better model 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 9
Example 1 q Calculate the effective carrier mobilities of n. MOS and p. MOS transistors when fully ON. Assume Vgs = 1 V, Vt = 0. 3 V and tox = 1. 05 nm 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 10
Example 2 q Find the critical voltage for n. MOS and p. MOS transistors that are fully ON, using the values obtained in example 1 and L = 50 nm. q (Hint Vc = Ec●L) q Which transistor is more vulnerable to velocity saturation? 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 11
Vel Sat I-V Effects q Ideal transistor ON current increases with VDD 2 q Velocity-saturated ON current increases with VDD q Real transistors are partially velocity saturated – Approximate with a-power law model – Ids VDDa – 1 < a < 2 determined empirically (≈ 1. 3 for 65 nm) 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 12
a-Power Model 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 13
Channel Length Modulation q Reverse-biased p-n junctions form a depletion region – Region between n and p with no carriers – Width of depletion Ld region grows with reverse bias – Leff = L – Ld q Shorter Leff gives more current – Ids increases with Vds – Even in saturation 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 14
Chan Length Mod I-V q l = channel length modulation coefficient – not feature size – Empirically fit to I-V characteristics 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 15
Threshold Voltage Effects q Vt is Vgs for which the channel starts to invert q Ideal models assumed Vt is constant q Really depends (weakly) on almost everything else: – Body voltage: Body Effect – Drain voltage: Drain-Induced Barrier Lowering – Channel length: Short Channel Effect 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 16
Body Effect q Body is a fourth transistor terminal q Vsb affects the charge required to invert the channel – Increasing Vs or decreasing Vb increases Vt q fs = surface potential at threshold q – Depends on doping level NA – And intrinsic carrier concentration ni g = body effect coefficient 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 17
Body Effect Cont. q For small source-to-body voltage, treat as linear 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 18
DIBL q Electric field from drain affects channel q More pronounced in small transistors where the drain is closer to the channel q Drain-Induced Barrier Lowering – Drain voltage also affect Vt q High drain voltage causes current to increase. 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 19
Short Channel Effect q In small transistors, source/drain depletion regions extend into the channel – Impacts the amount of charge required to invert the channel – And thus makes Vt a function of channel length q Short channel effect: Vt increases with L – Some processes exhibit a reverse short channel effect in which Vt decreases with L 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 20
Leakage q What about current in cutoff? q Simulated results q What differs? – Current doesn’t go to 0 in cutoff 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 21
Leakage Sources q Subthreshold conduction – Transistors can’t abruptly turn ON or OFF – Dominant source in contemporary transistors q Gate leakage – Tunneling through ultrathin gate dielectric q Junction leakage – Reverse-biased PN junction diode current 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 22
Subthreshold Leakage q Subthreshold leakage exponential with Vgs q n is process dependent – typically 1. 3 -1. 7 q Rewrite relative to Ioff on log scale q S ≈ 100 m. V/decade @ room temperature 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 23
Gate Leakage q Carriers tunnel through very thin gate oxides q Exponentially sensitive to tox and VDD – A and B are tech constants – Greater for electrons • So n. MOS gates leak more q Negligible for older processes (tox > 20 Å) q Critically important at 65 nm and below (tox ≈ 10. 5 Å) From [Song 01] 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 24
Junction Leakage q Reverse-biased p-n junctions have some leakage – Ordinary diode leakage – Band-to-band tunneling (BTBT) – Gate-induced drain leakage (GIDL) 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 25
Diode Leakage q Reverse-biased p-n junctions have some leakage q At any significant negative diode voltage, ID = -Is q Is depends on doping levels – And area and perimeter of diffusion regions – Typically < 1 f. A/mm 2 (negligible) 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 26
Band-to-Band Tunneling q Tunneling across heavily doped p-n junctions – Especially sidewall between drain & channel when halo doping is used to increase Vt q Increases junction leakage to significant levels – Xj: sidewall junction depth – Eg: bandgap voltage – A, B: tech constants 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 27
Gate-Induced Drain Leakage q Occurs at overlap between gate and drain – Most pronounced when drain is at VDD, gate is at a negative voltage – Thwarts efforts to reduce subthreshold leakage using a negative gate voltage 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 28
Temperature Sensitivity q Increasing temperature – Reduces mobility – Reduces Vt q ION decreases with temperature q IOFF increases with temperature 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 29
So What? q So what if transistors are not ideal? – They still behave like switches. q But these effects matter for… – Supply voltage choice – Logical effort – Quiescent power consumption – Pass transistors – Temperature of operation 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 30
Parameter Variation q Transistors have uncertainty in parameters – Process: Leff, Vt, tox of n. MOS and p. MOS – Vary around typical (T) values q Fast (F) – Leff: short – Vt: low – tox: thin q Slow (S): opposite q Not all parameters are independent for n. MOS and p. MOS 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 31
Environmental Variation q VDD and T also vary in time and space q Fast: – VDD: high – T: low Corner Voltage Temperature F 1. 98 0 C T 1. 8 70 C S 1. 62 125 C 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 32
Process Corners q Process corners describe worst case variations – If a design works in all corners, it will probably work for any variation. q Describe corner with four letters (T, F, S) – n. MOS speed – p. MOS speed – Voltage – Temperature 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 33
Important Corners q Some critical simulation corners include Purpose n. MOS p. MOS VDD Temp Cycle time S S Power F F Subthreshold leakage F F F S 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 34
Example 3 q Consider an n. MOS transistor manufactured in 65 nm process, with nominal threshold voltage equal to 0. 3 V and doping levels of 8 x 10^17 cm^(-3). The substrate is connected to ground with a contact. What will be the change in the treshold voltage at room temperature if the sourse is at 0. 6 V instead of 0 V? q (Assume tox = 1. 05 nm, q=1. 6 x 10^(-19) Cb, v. T = k. T/q = 26 m. V, ni = 1. 45 x 10^10 cm^(-3), εox = 3. 9 x 8. 85 x 10^(-14) F/cm, εSi = 11. 7 x 8. 85 x 10^(-14) F/cm) 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 35
Example 4 q An n. MOS transistor has a threshold voltage of 0. 4 V and Vdd = 1. 2 V. A designer considers reducing the threshold voltage by 100 m. V in order to increase transistor speed q (i) By how much would the saturation current increase (for Vgs=Vdd) if the transistors were ideal? q (ii) By how much would the subthreshold leakage current increase in room temperature for Vgs=0; Assume n=1. 4 q (iii) By how much would the subthreshold leakage current increase at 120°C? q Assume that Vt is constant. q k=1. 380 6504(24)× 10− 23 J/K 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 36
Example 5 q Find the subthreshold leakage current of an inverter at room temperature if the input A=0. Let βn=2βp = 1 m. A/V^2. , n=1. 4, and ABS(Vt)=0. 4 V. Assume the body effect and DIBL coefficients are zero. 4: Nonideal Transistor Theory CMOS VLSI Design 4 th Ed. 37
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