Lecture 23 OUTLINE The MOSFET contd Sourcedrain structure

Lecture 23 OUTLINE The MOSFET (cont’d) • Source/drain structure • CMOS fabrication process • The CMOS power crisis Reading: Pierret 19. 2; Hu 6. 10 Optional Reading: Pierret 4; Hu 3

Source and Drain (S/D) Structure • To minimize the short channel effect and DIBL, we want shallow (small rj) S/D regions but the parasitic resistance of these regions increases when rj is reduced. where r = resistivity of the S/D regions • Shallow S/D “extensions” may be used to effectively reduce rj with a relatively small increase in parasitic resistance EE 130/230 A Fall 2013 Lecture 23, Slide 2

E-Field Distribution Along the Channel • The lateral electric field peaks at the drain end of the channel. Epeak can be as high as 106 V/cm • High E-field causes problems: –Damage to oxide interface & bulk (trapped oxide charge VT shift) –substrate current due to impact ionization: EE 130/230 A Fall 2013 Lecture 23, Slide 3

Lightly Doped Drain (LDD) Structure • Lower pn junction doping results in lower peak E-field ü “Hot-carrier” effects are reduced û Parasitic resistance is increased R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19. 9 EE 130/230 A Fall 2013 Lecture 23, Slide 4

Parasitic Source-Drain Resistance G RS S RD D • For short-channel MOSFET, IDsat 0 VGS – VT , so that IDsat is reduced by ~15% in a 0. 1 mm MOSFET. • VDsat is increased to VDsat 0 + IDsat (RS + RD) EE 130/230 A Fall 2013 Lecture 23, Slide 5 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 7 -10

Summary: MOSFET OFF State vs. ON State • OFF state (VGS < VT): – IDS is limited by the rate at which carriers diffuse across the source pn junction – Minimum subthreshold swing S, and DIBL are issues • ON state (VGS > VT): – IDS is limited by the rate at which carriers drift across the channel – Punchthrough is of concern at high drain bias • IDsat increases rapidly with VDS – Parasitic resistances reduce drive current • source resistance RS reduces effective VGS • source & drain resistances RS & RD reduce effective VDS EE 130/230 A Fall 2013 Lecture 23, Slide 6

CMOS Technology Need p-type regions (for NMOS) and n-type regions (for PMOS) on the wafer surface, e. g. : (ND) n-well (NA) Single-well technology • n-well must be deep enough to avoid vertical punch-through p-substrate (NA) p-well Twin-well technology • Wells must be deep enough to avoid vertical punch-through (ND) n-well p- or n-substrate (lightly doped) EE 130/230 A Fall 2013 Lecture 23, Slide 7

Sub-Micron CMOS Fabrication Process • A series of lithography, etch, and fill steps are used to create silicon mesas isolated by silicon -dioxide • Lithography and implant steps are used to form the NMOS and PMOS wells and the channel/body doping profiles EE 130/230 A Fall 2013 Lecture 23, Slide 8

• The thin gate dielectric layer is formed • Poly-Si is deposited and patterned to form gate electrodes • Lithography and implantation are used to form NLDD and PLDD regions EE 130/230 A Fall 2013 Lecture 23, Slide 9

• A series of steps is used to form the deep source / drain regions as well as body contacts • A series of steps is used to encapsulate the devices and form metal interconnections between them. EE 130/230 A Fall 2013 Lecture 23, Slide 10

CMOS Technology Advancement XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc. ) 90 nm node T. Ghani et al. , IEDM 2003 65 nm node (after S. Tyagi et al. , IEDM 2005) 45 nm node 32 nm node K. Mistry et al. , IEDM 2007 P. Packan et al. , IEDM 2009 • Gate length has not scaled proportionately with device pitch (0. 7 x per generation) in recent generations. – Transistor performance has been boosted by other means. EE 130/230 A Fall 2013 Lecture 23, Slide 11

Performance Boosters • Strained channel regions meff • High-k gate dielectric and metal gate electrodes Coxe Cross-sectional TEM views of Intel’s 32 nm CMOS devices P. Packan et al. , IEDM Technical Digest, pp. 659 -662, 2009 EE 130/230 A Fall 2013 Lecture 23, Slide 12

Historical Voltage Scaling • Since VT cannot be scaled down aggressively, the supply voltage (VDD) has not been scaled down in proportion to the MOSFET gate length: VDD – VT Source: P. Packan (Intel), 2007 IEDM Short Course EE 130/230 A Fall 2013 Lecture 23, Slide 13

Power Density Scaling – NOT! 1 E+03 Power Density Prediction circa 2000 Power Density (W/cm 2) Power Density Trend Active Power Density 1 E+02 1 E+01 1 E+00 1 E-01 1 E-02 1 E-03 1 E-04 Passive Power Density 1 E-05 0. 01 0. 1 Gate Length (μm) 1 10000 100 Rocket Nozzle Nuclear Reactor 8086 Hot Plate 10 4004 P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 Year Source: S. Borkar (Intel ) Source: B. Meyerson (IBM) Semico Conf. , January 2004 EE 130/230 A Fall 2013 Sun’s Surface Lecture 23, Slide 14 2010

Parallelism • Computing performance is now limited by power dissipation. This has forced the move to parallelism as the principal means of increasing system performance. Energy vs. Delay per operation Power Density (W/cm 2) 10000 100 single core Sun’s Surface Rocket Nozzle dual core Nuclear Reactor Core 2 8086 Hot Plate 10 4004 P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Source: S. Borkar (Intel ) EE 130/230 A Fall 2013 Lecture 23, Slide 15 Operate at a lower energy point (lower VDD) Run in parallel to recoup performance

Key to VDD Reduction: Gate Control Gate log ID ION Cox Cdep Source Body Drain VDD VGS • The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential. lower VDD to achieve target ION/IOFF reduced short-channel effect (SCE) and drain-induced barrier lowering (DIBL) EE 130/230 A Fall 2013 Lecture 23, Slide 16

Intel Ivy Bridge Processor EE 130/230 A Fall 2013 Lecture 23, Slide 17