Lecture 22 OUTLINE Timing diagrams Delay Analysis Reading

Lecture #22 OUTLINE » Timing diagrams » Delay Analysis Reading (Rabaey et al. ) • Chapter 5. 4 • Chapter 6. 2. 1, pp. 260 -263 EECS 40, Fall 2004 Lecture 22, Slide 1 Prof. White

Propagation Delay in Timing Diagrams • To simplify the drawing of timing diagrams, we can approximate the signal transitions to be abrupt (though in reality they are exponential). A A F F 1 0 t tp. HL tp. LH t To further simplify timing analysis, we can define the propagation delay as EECS 40, Fall 2004 Lecture 22, Slide 2 Prof. White

Glitching Transitions A, B, C The propagation delay from one logic gate to the next can cause spurious transitions, called glitches, to occur. (A node can exhibit multiple transitions before settling to the correct logic level. ) 1 0 B 1 0 t B • C 1 0 A+B A B t tp 2 tp 3 tp t A+B F B C EECS 40, Fall 2004 1 0 t F B • C Lecture 22, Slide 3 1 0 t Prof. White

Glitch Reduction • Spurious transitions can be minimized by balancing signal paths Example: F = A • B • C • D EECS 40, Fall 2004 Lecture 22, Slide 4 Prof. White

MOSFET Layout and Cross-Section Top View: Cross Section: EECS 40, Fall 2004 Lecture 22, Slide 5 Prof. White

Source and Drain Junction Capacitance Csource = Cj (AREA) + Cjsw (PERIMETER) = Cj. LSW + CJSW(2 LS + W) EECS 40, Fall 2004 Lecture 22, Slide 6 Prof. White

Computing the Output Capacitance 2 l=0. 25 mm Example 5. 4 (pp. 197 -203) VDD In Out PMOS W/L=9 l/2 l Poly-Si Out In NMOS W/L=3 l/2 l GND Metal 1 EECS 40, Fall 2004 Lecture 22, Slide 7 Prof. White

2 l=0. 25 mm VDD PMOS Capacitances for 0. 25 mm technology: W/L=9 l/2 l Gate capacitances: • Cox(NMOS) = Cox(PMOS) = 6 f. F/mm 2 Overlap capacitances: In • CGDO(NMOS) = Con = 0. 31 f. F/mm • CGDO(PMOS)= Cop = 0. 27 f. F/mm Bottom junction capacitances: • CJ(NMOS) = Keqbpn. Cj = 2 f. F/mm 2 NMOS • CJ(PMOS) = Keqbpp. Cj = 1. 9 f. F/mm 2 W/L=3 l/2 l Sidewall junction capacitances: GND • CJSW(NMOS) = Keqswn. Cj = 0. 28 f. F/mm • CJSW(PMOS) = Keqbpp. Cj = 0. 22 f. F/mm EECS 40, Fall 2004 Lecture 22, Slide 8 Out Prof. White

EECS 40, Fall 2004 Lecture 22, Slide 9 Prof. White

Typical MOSFET Parameter Values • For a given MOSFET fabrication process technology, the following parameters are known: – – VT (~0. 5 V) Cox and k (<0. 001 A/V 2) VDSAT ( 1 V) l ( 0. 1 V-1) Example Req values for 0. 25 mm technology (W = L): EECS 40, Fall 2004 Lecture 22, Slide 10 Prof. White

Compute propagation delays EECS 40, Fall 2004 Lecture 22, Slide 11 Prof. White

Examples of Propagation Delay Pentium II CMOS technology generation 0. 25 mm Pentium III Pentium IV Product 600 MHz Fan-out=4 inverter delay ~100 ps 0. 18 mm 1. 8 GHz ~40 ps 0. 13 mm 3. 2 GHz ~20 ps Clock frequency, f Typical clock periods: • high-performance m. P: ~15 FO 4 delays • Play. Station 2: 60 FO 4 delays EECS 40, Fall 2004 Lecture 22, Slide 12 Prof. White

STATIC CMOS DRIVING LARGE LOADS VDD MP 1 vin + - vout CL MN 1 The load, CL , may be the capacitance of a long line on the chip (e. g. up to 1 p. F, or may be the load on one of the chip output pins (e. g. up to 50 p. F). We have seen that the typical driving resistance R for a minimum sized inverter is in the range of 10 KW. A 1 KW resistor driving a 50 p. F load would have a stage delay of 35 nsec, huge in comparison to normal stage delays. Thus we need to use larger devices to drive large capacitive loads, that is greatly increase W/L. However, increasing W/L of a stage will increase the load it presents to the stage driving it, and we just move the delay problem back one stage. EECS 40, Fall 2004 Lecture 22, Slide 13 Prof. White

STATIC CMOS DRIVING LARGE LOADS VDD MP 1 VDD PROBLEM: A minimum sized inverter drives a large load, CL, leading to excessive delay, even with a buffer stage. MPB vout vin + - CL PROPOSED SOLUTION: Insert MNB several simple inverter stages with MN 1 increasing W/L between Inverter 1 and the load CL. The total delay through the multiple stages will be less than the delay of one single stage driving CL. VDD MP 1 MPB 2 MPB 3 vout vin + - CL MN 1 EECS 40, Fall 2004 MNB 1 MNB 2 Lecture 22, Slide 14 MNB 3 Prof. White

STATIC CMOS DRIVING LARGE LOADS Example: The 2. 5 V 0. 25 mm CMOS inverter driving 50 p. F load. Properties: W/L|N =1/. 25, W/L|P =2/. 25, VDD = 2. 5 V, VT = 0. 5 V. Rn = 13 KW /4 = 3. 25 KW ; Rp = 31 KW /8 = 3. 75 KW 5 nm oxide thickness , Cox =6. 9 f. F/mm 2. NMOS: CGp = W x L x Cox =1. 7 f. F. PMOS : CGp = W x L x Cox =3. 4 f. F. Thus CIN= 5. 2 f. F Basic gate delay (0. 69 RC) is about 10 p. S. If we size one inverter to drive the load with this time constant it requires a W/L increase by a factor of 50 p. F/5. 2 f. F =9615. So CIN= 50000 f. F =50 p. F for the buffer gate! Thus the gate delay for the first stage is (50000/5. 2)X 10 p. S = 96. 1 n. S. Total delay = 96. 1 +. 01 = 96. 11 n. S. TOO LONG and NO IMPROVEMENT! Note: We are ignoring drain capacitance in these examples. EECS 40, Fall 2004 vin VDD MP 1 MPB vout + - W/L = 4 Lecture 22, Slide 15 MN 1 MNB 50 p. F W/L = 9615 Prof. White

STATIC CMOS DRIVING LARGE LOADS Same example with tapered device sizes (geometric series) Case 1: Same example, but with buffer devices scaled by factor of 98 (982=9615 ) Stage 1 load = 98 X 5. 2 f. F, (R= 3. 5 K) Stage 2 load = 50 p. F , (R = 3. 5 K /98) Delay = 98 X 10 p. S + 96 n. S/98 =0. 98 +0. 98 n. S ~2 n. S Case 2: Now taper through 3 buffer stages with W/L ratios of 9. 9 (9. 94=9615) VDD MP 1 MPB 2 MPB 3 vout vin + - CL MN 1 MNB 2 MNB 3 4 equal gate delays of 9. 9 x 10 p. S =99 p. S Total = 4 X. 099 n. S ~0. 4 n. S Gate delay through 4 gates is much less than through 2! Note: We are ignoring drain capacitance in these examples. EECS 40, Fall 2004 Lecture 22, Slide 16 Prof. White

STATIC CMOS DRIVING LARGE LOADS Comments In our example we got better results with 3 buffer stages than 1. 7 buffer stages would do even better. How many buffer stages are optimum? Well under these simple assumptions (like ignoring drain and wiring capacitance, and operating asynchronously) you can show that the number of buffer stages, N obeys N +1 = ln(R) where R is the ratio of the load capacitance to the capacitance of a minimum sized stage. This formula is not important, but you should remember the concept that buffering with multiple stages usually leads to lower net delay if the load is large. VDD MP 1 MPB 2 MPB 3 vout vin + - CL MN 1 EECS 40, Fall 2004 MNB 1 MNB 2 Lecture 22, Slide 17 MNB 3 Prof. White