# Lecture 20 ANNOUNCEMENTS HW11 is due in 2

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Lecture 20 ANNOUNCEMENTS • HW#11 is due in 2 weeks, on 11/20. • Review session: Fri. 11/9, 3 -5 PM in 306 Soda (HP Auditorium) • Midterm #2 (Thursday 11/15 in Sibley Auditorium): • Material of Lectures 11 -18 (HW# 7 -10; Chapters 6, 9, 11) • 4 pgs of notes (double-sided, 8. 5”× 11”), calculator allowed OUTLINE • Review of MOSFET Amplifiers • MOSFET Cascode Stage • MOSFET Current Mirror Reading: Chapter 9 EE 105 Fall 2007 Lecture 20, Slide 1 Prof. Liu, UC Berkeley

Review: MOSFET Amplifier Design • A MOSFET amplifier circuit should be designed to 1. ensure that the MOSFET operates in the saturation region, 2. allow the desired level of DC current to flow, and 3. couple to a small-signal input source and to an output “load”. à Proper “DC biasing” is required! (DC analysis using large-signal MOSFET model) • Key amplifier parameters: (AC analysis using small-signal MOSFET model) – Voltage gain Av vout/vin – Input resistance Rin resistance seen between the input node and ground (with output terminal floating) – Output resistance Rout resistance seen between the output node and ground (with input terminal grounded) EE 105 Fall 2007 Lecture 20, Slide 2 Prof. Liu, UC Berkeley

MOSFET Models • The large-signal model is used to determine the DC operating point (VGS, VDS, ID) of the MOSFET. • The small-signal model is used to determine how the output responds to an input signal. EE 105 Fall 2007 Lecture 20, Slide 3 Prof. Liu, UC Berkeley

Comparison of Amplifier Topologies Common Source • Large Av < 0 - degraded by RS • Large Rin Common Gate • Large Av > 0 -degraded by RS • Small Rin - decreased by RS – determined by biasing circuitry • Rout RD • ro decreases Av & Rout but impedance seen looking into the drain can be “boosted” by source degeneration EE 105 Fall 2007 • ro decreases Av & Rout but impedance seen looking into the drain can be “boosted” by source degeneration Lecture 20, Slide 4 Source Follower • 0 < Av ≤ 1 • Large Rin – determined by biasing circuitry • Small Rout - decreased by RS • ro decreases Av & Rout Prof. Liu, UC Berkeley

Common Source Stage EE 105 Fall 2007 Lecture 20, Slide 5 Prof. Liu, UC Berkeley

Common Gate Stage EE 105 Fall 2007 Lecture 20, Slide 6 Prof. Liu, UC Berkeley

Source Follower EE 105 Fall 2007 Lecture 20, Slide 7 Prof. Liu, UC Berkeley

CS Stage Example 1 • M 1 is the amplifying device; M 2 and M 3 serve as the load. Equivalent circuit for small-signal analysis, showing resistances connected to the drain EE 105 Fall 2007 Lecture 20, Slide 8 Prof. Liu, UC Berkeley

CS Stage Example 2 • M 1 is the amplifying device; M 3 serves as a source (degeneration) resistance; M 2 serves as the load. Equivalent circuit for small-signal analysis EE 105 Fall 2007 Lecture 20, Slide 9 Prof. Liu, UC Berkeley

CS Stage vs. CG Stage • With the input signal applied at different locations, these circuits behave differently, although they are identical in other aspects. Common gate amplifier Common source amplifier EE 105 Fall 2007 Lecture 20, Slide 10 Prof. Liu, UC Berkeley

Composite Stage Example 1 • By replacing M 1 and the current source with a Thevenin equivalent circuit, and recognizing the right side as a CG stage, the voltage gain can be easily obtained. EE 105 Fall 2007 Lecture 20, Slide 11 Prof. Liu, UC Berkeley

Composite Stage Example 2 • This example shows that by probing different nodes in a circuit, different output signals can be obtained. • Vout 1 is a result of M 1 acting as a source follower, whereas Vout 2 is a result of M 1 acting as a CS stage with degeneration. EE 105 Fall 2007 Lecture 20, Slide 12 Prof. Liu, UC Berkeley

NMOS Cascode Stage • Unlike a BJT cascode, the output impedance is not limited by . EE 105 Fall 2007 Lecture 20, Slide 13 Prof. Liu, UC Berkeley

PMOS Cascode Stage EE 105 Fall 2007 Lecture 20, Slide 14 Prof. Liu, UC Berkeley

Short-Circuit Transconductance • The short-circuit transconductance is a measure of the strength of a circuit in converting an input voltage signal into an output current signal: • The voltage gain of a linear circuit is (Rout is the output resistance of the circuit) EE 105 Fall 2007 Lecture 20, Slide 15 Prof. Liu, UC Berkeley

Transconductance Example EE 105 Fall 2007 Lecture 20, Slide 16 Prof. Liu, UC Berkeley

MOS Cascode Amplifier EE 105 Fall 2007 Lecture 20, Slide 17 Prof. Liu, UC Berkeley

PMOS Cascode Current Source as Load • A large load impedance can be achieved by using a PMOS cascode current source. EE 105 Fall 2007 Lecture 20, Slide 18 Prof. Liu, UC Berkeley

MOS Current Mirror • The motivation behind a current mirror is to duplicate a (scaled version of the) “golden current” to other locations. Current mirror concept EE 105 Fall 2007 Generation of required VGS Lecture 20, Slide 19 Current Mirror Circuitry Prof. Liu, UC Berkeley

MOS Current Mirror – NOT! • This is not a current mirror, because the relationship between VX and IREF is not clearly defined. • The only way to clearly define VX with IREF is to use a diodeconnected MOS since it provides square-law I-V relationship. EE 105 Fall 2007 Lecture 20, Slide 20 Prof. Liu, UC Berkeley

Example: Current Scaling • MOS current mirrors can be used to scale IREF up or down – I 1 = 0. 2 m. A; I 2 = 0. 5 m. A EE 105 Fall 2007 Lecture 20, Slide 21 Prof. Liu, UC Berkeley

Impact of Channel-Length Modulation EE 105 Fall 2007 Lecture 20, Slide 22 Prof. Liu, UC Berkeley

CMOS Current Mirror EE 105 Fall 2007 Lecture 20, Slide 23 Prof. Liu, UC Berkeley