Lecture 19 Programmable Logic Memories Recommended reading Vivado

Lecture 19 Programmable Logic Memories

Recommended reading • Vivado Design Suite User Guide: Synthesis Chapter 4 • RAM HDL Coding Techniques • Initializing RAM Contents • 7 Series FPGAs Memory Resources: User Guide • Chapter 1: Block RAM Resources • 7 Series FPGAs Configurable Logic Block: User Guide • Chapter 2: Functional Details: Distributed RAM 2

Memory Types 3

Memory Types Memory ROM RAM Memory Single port Dual port Memory With asynchronous read With synchronous read 4

Memory Types specific to Xilinx FPGAs Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using Vivado 5

FPGA Distributed Memory

Location of Distributed RAM Logic resources (CLB slices) RAM blocks DSP units Logic resources Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www. mentor. com) 7

SLICEL 8

SLICEM ECE 448 – FPGA and ASIC Design with VHDL 9

Xilinx Multipurpose LUT (MLUT) 32 -bit SR 64 x 1 RAM 64 x 1 ROM (logic) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www. mentor. com) 10

Single-port 64 x 1 -bit RAM 11

Single-port 64 x 1 -bit RAM 12

Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: • Single-port 128 x 1 -bit RAM: • Dual-port 64 x 1 -bit RAM : RAM 128 x 1 S RAM 64 x 1 D Memories built of 4 MLUTs: • • Single-port 256 x 1 -bit RAM: RAM 256 x 1 S Dual-port 128 x 1 -bit RAM: RAM 128 x 1 D Quad-port 64 x 1 -bit RAM: RAM 64 x 1 Q Simple-dual-port 64 x 3 -bit RAM: RAM 64 x 3 SDP (one address for read, one address for write) 13

Dual-port 64 x 1 RAM • • Dual-port 64 x 1 -bit RAM : Single-port 128 x 1 -bit RAM: 64 x 1 D 128 x 1 S 14

Dual-port 64 x 1 RAM • • Dual-port 64 x 1 -bit RAM : Single-port 128 x 1 -bit RAM: 64 x 1 D 128 x 1 S 15

FPGA Block RAM 16

Location of Block RAMs Logic resources (CLB slices) RAM blocks DSP units Logic resources Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www. mentor. com) 17

Block RAM Configured as 1 x 36 kbit RAM or 2 x 18 kbit RAMs 18

Block RAM Simple Dual Port (SDP) = one port for read, one port for write (write_A-read_B or read_A_write_B) True Dual Port (TDP) = both ports can be used for read or write (read_A-read_B, read_A-write_B, write_A-read_B, write_A-write_B) 19

Block RAM can have various configurations (port aspect ratios) 1 2 0 4 0 0 4 k x 4 8 k x 2 4, 095 16 k x 1 8, 191 8+1 0 2 k x (8+1) 2047 16+2 0 1023 1024 x (16+2) 16, 383 20

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18 k Block RAM Port Aspect Ratios 23

Block RAM Interface 24

Block RAM Ports 25

Cascadable Block RAM 26

Block RAM Waveforms – READ_FIRST mode 27

Block RAM Waveforms – WRITE_FIRST mode 28

Block RAM Waveforms – NO_CHANGE mode 29

Features of Block RAMs 30

Inference vs. Instantiation 31

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Generic Inferred ROM 33

Distributed ROM with asynchronous read LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. numeric_std. all; Entity ROM is generic ( w : integer : = 12; -- number of bits per ROM word r : integer : = 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM; 34

Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type : = ("000011000100", "010011010010", "010011011011", "011011000010", "000011110001", "011111010110", "010011010000", "111110011111"); begin dout <= ROM_array(to_integer(unsigned(addr))); end behavioral; 35

Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type : = (X"0 C 4", X"4 D 2", X"4 DB", X"6 C 2", X"0 F 1", X"7 D 6", X"4 D 0", X"F 9 F"); begin dout <= ROM_array(to_integer(unsigned(addr))); end behavioral; 36

Generic Inferred RAM 37

Distributed versus Block RAM Inference Examples: 1. Distributed single-port RAM with asynchronous read 2. Distributed dual-port RAM with asynchronous read 3. Block RAM with synchronous read (no version with asynchronous read!) More RAM examples in Vivado Design Suite User Guide: Synthesis 38

Distributed single-port RAM with asynchronous read LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. numeric_std. all; entity raminfr is generic ( w : integer : = 32; -- number of bits per RAM word r : integer : = 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 39

Distributed single-port RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type : = (others => '0')); begin process (clk) begin if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end if; end process; do <= RAM(to_integer(unsigned(a))); end behavioral; 40

Distributed dual-port RAM with asynchronous read library ieee; use ieee. std_logic_1164. all; use ieee. numeric_std. all; entity raminfr is generic ( w : integer : = 32; -- number of bits per RAM word r : integer : = 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr; 41

Distributed dual-port RAM with asynchronous read architecture syn of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type : = (others => '0')); begin process (clk) begin if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end if; end process; spo <= RAM(to_integer(unsigned(a))); dpo <= RAM(to_integer(unsigned(dpra))); end syn; 42

Block RAM Waveforms – READ_FIRST mode 43

Block RAM with synchronous read LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. numeric_std. all; entity raminfr is generic ( w : integer : = 32; -- number of bits per RAM word r : integer : = 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 44

Block RAM with synchronous read Read-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type : = (others => '0')); begin process (clk) begin if rising_edge(clk) then if (en = '1') then do <= RAM(to_integer(unsigned(addr))); if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; end if; end process; end behavioral; 45

Block RAM Waveforms – WRITE_FIRST mode 46

Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type : = (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end process; end behavioral; 47

Block RAM Waveforms – NO_CHANGE mode 48

Block RAM with synchronous read No-Change Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type : = (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end process; end behavioral; 49

Criteria for Implementing Inferred RAM in BRAMs 50

FIFOs 51

FIFO Interface clk rst FIFO din dout 8 8 full write ECE 448 – FPGA and ASIC Design with VHDL empty read 52

Operation of the “Standard” FIFO −−−−− A B C D 53

Operation of the First-Word Fall-Through FIFO 54