Lecture 18 SORTING in Hardware Sorting LED Switches

Lecture 18 SORTING in Hardware

Sorting LED Switches GPO 2 GPI 2 SSEG Buttons

Sorting - Required Interface Clock Resetn N N Data. In RAdd Data. Out L Wr. Init S (0=initialization 1=computations) Rd Sort Done

Sorting - Required Interface

Simulation results for the sort operation (1) Loading memory and starting sorting

Simulation results for the sort operation (2) Completing sorting and reading out memory

Sorting - Example Before sorting Address 0 1 2 3 Legend: 3 2 4 1 During Sorting i=0 j=1 i=0 j=2 i=0 j=3 i=1 j=2 i=1 j=3 i=2 j=3 3 2 4 1 2 3 4 1 1 3 4 2 1 2 4 3 position of memory indexed by i Mi position of memory indexed by j After sorting 1 2 3 4 Mj

Pseudocode FOR k = 4 [load input data] wait for s=1 for i = 0 to 2 do A = Mi ; for j = i + 1 to 3 do B = Mj ; if B < A then Mi = B ; Mj = A ; A = Mi ; endif ; endfor; Done wait for s=0 [read output data] go to the beginning FOR any k ≥ 2 [load input data] wait for s=1 for i = 0 to k -2 do A = Mi ; for j = i + 1 to k – 1 do B = Mj ; if B < A then Mi = B ; Mj = A ; A = Mi ; endif ; endfor; Done wait for s=0 [read output data] go to the beginning

Pseudocode wait for s=1 for i=0 to k-2 do A = Mi for j=i+1 to k-1 do B = Mj if A > B then Mi = B Mj = A A = Mi end if end for Done wait for s=0 go to the beginning

Structure of a Typical Digital System Data Inputs Datapath (Execution Unit) Control Inputs Control Signals Controller (Control Unit) Status Signals Data Outputs Control Outputs

Hardware Design with RTL VHDL Pseudocode Datapath Interface Controller Block diagram VHDL code ASM chart VHDL code

Steps of the Design Process 1. 2. 3. 4. 5. 6. 7. Text description Interface Pseudocode Block diagram of the Datapath Interface divided into the Datapath and Controller ASM chart of the Controller RTL VHDL code of the Datapath, Controller, and Top-level Unit 8. Testbench for the Datapath, Controller, and Top. Level Unit 9. Functional simulation and debugging 10. Integration with the FPro System – – Hardware Software 11. Synthesis and Implementation 12. Experimental testing using FPGA board 12

Contest for the Fastest Implementation of Sorting Bonus points will be awarded to students who perform sorting (correctly) using the smallest number of clock cycles in hardware and/or software Possible optimizations: • Faster sorting algorithms in software • Efficient C implementation • Faster sorting algorithms in hardware • Efficient VHDL implementation

SORTING solutions

Block diagram of the Datapath

Data. In ABMux RAdd 1 s 0 Ei s 0 We Clock DIN WE RST EB EN CLK Bout RST N N 0 Ej Lj Clock EN LD CLK RST L j 1 Mij Clock L L i 0 1 Resetn +1 0 Addr CLK N EN CLK RST Csel DOUT EA Clock s ADDR 1 Wr EN LD CLK Li Din Wr. Init L L N 1 0 N Resetn Rd = k-2 = k-1 zi zj N B A A>B Agt. B Data. Out Block diagram of the Datapath Resetn

Interface with the division into the Datapath and Controller Data. In RAddr Wr. Init N Rd Clock Resetn s L Datapath Agt. B zi zj Wr Li Ei Lj Ej EA EB Bout Csel Controller N Data. Out Done

ASM Chart of the Controller

Timing Waveforms Explaining the Need for State S 3