Lecture 13 Sequential Circuit ATPG TimeFrame Expansion Lecture

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Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12 alt in the Alternative Sequence)

Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12 alt in the Alternative Sequence) n n Problem of sequential circuit ATPG Time-frame expansion n n n Nine-valued logic ATPG implementation and drivability Complexity of ATPG Cycle-free and cyclic circuits Asynchronous circuits Summary and Exercise Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 1

Sequential Circuits n n A sequential circuit has memory in addition to combinational logic.

Sequential Circuits n n A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which n n Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Methods of sequential circuit ATPG n n Time-frame expansion methods Simulation-based methods Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 2

Example: A Serial Adder An Bn 1 1 s-a-0 D 1 1 D Cn

Example: A Serial Adder An Bn 1 1 s-a-0 D 1 1 D Cn X Cn+1 X 1 Combinational logic FF Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt Sn X 3

Time-Frame Expansion An-1 Bn-1 1 1 An Bn Time-frame -1 s-a-0 D 1 1

Time-Frame Expansion An-1 Bn-1 1 1 An Bn Time-frame -1 s-a-0 D 1 1 X 1 Cn-1 Time-frame 0 s-a-0 D D 1 1 D X Cn X 1 D 1 Cn+1 1 Combinational logic Sn-1 1 Sn X D FF Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 4

Concept of Time-Frames n If the test sequence for a single stuck-at fault contains

Concept of Time-Frames n If the test sequence for a single stuck-at fault contains n vectors, n n n Fault Unknown or given Init. state Comb. block Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9 -valued logic Vector – n +1 Time. State Frame variables - n+1 PO – n +1 Copyright 2001, Agrawal & Bushnell Vector – 1 Vector 0 Timeframe -1 Timeframe 0 PO – 1 VLSI Test: Lecture 13/12 alt Next state PO 0 5

Example for Logic Systems FF 1 A s-a-1 Copyright 2001, Agrawal & Bushnell B

Example for Logic Systems FF 1 A s-a-1 Copyright 2001, Agrawal & Bushnell B FF 2 VLSI Test: Lecture 13/12 alt 6

Five-Valued Logic (Roth) 0, 1, D, D, X A 0 s-a-1 D FF 1

Five-Valued Logic (Roth) 0, 1, D, D, X A 0 s-a-1 D FF 1 FF 2 D X X D D Time-frame -1 Copyright 2001, Agrawal & Bushnell B X Time-frame 0 VLSI Test: Lecture 13/12 alt B FF 1 FF 2 X 7

Nine-Valued Logic (Muth) 0, 1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X A 0

Nine-Valued Logic (Muth) 0, 1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X A 0 A s-a-1 X/1 0/1 FF 2 X X 0/X X 0/1 X/1 Time-frame -1 Copyright 2001, Agrawal & Bushnell B X Time-frame 0 VLSI Test: Lecture 13/12 alt B FF 1 FF 2 0/1 8

Implementation of ATPG n n n Select a PO for fault detection based on

Implementation of ATPG n n n Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the fault is potentially detectable. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 9

Drivability Example (11, 16) s-a-1 8 d(0/1) = d(1/0) = 20 8 d(0/1) =

Drivability Example (11, 16) s-a-1 8 d(0/1) = d(1/0) = 20 8 d(0/1) = 4 d(1/0) = (4, 4) (10, 16) d(0/1) = 9 d(1/0) = 8 (CC 0, CC 1) = (6, 4) (5, 9) (22, 17) d(0/1) = d(1/0) = 32 8 (10, 15) (17, 11) FF (6, 10) d(0/1) = 120 d(1/0) = 27 8 d(0/1) = 109 d(1/0) = CC 0 and CC 1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 10

Complexity of ATPG § Synchronous circuit -- All flip-flops controlled by clocks; PI and

Complexity of ATPG § Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: § Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 timeframes, where dseq is the sequential depth. § Cyclic circuit – Contains feedback among flip-flops: May need 9 Nff time-frames, where Nff is the number of flipflops. Asynchronous circuit – Higher complexity! § Smax Time. Frame max-1 Time. Frame max-2 S 3 Time- S 2 Time- S 1 Time- S 0 Frame -2 -1 0 max = Number of distinct vectors with 9 -valued elements = 9 Nff Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 11

Cycle-Free Circuits n n Characterized by absence of cycles among flipflops and a sequential

Cycle-Free Circuits n n Characterized by absence of cycles among flipflops and a sequential depth, dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 12

Cycle-Free Example Circuit F 2 2 F 3 F 1 Level = 1 3

Cycle-Free Example Circuit F 2 2 F 3 F 1 Level = 1 3 F 2 All faults are testable in this circuit. 2 s - graph F 1 F 3 Level = 1 3 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt dseq = 3 13

Cyclic Circuit Example Modulo-3 counter CNT F 2 F 1 Z s - graph

Cyclic Circuit Example Modulo-3 counter CNT F 2 F 1 Z s - graph F 2 F 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 14

Modulo-3 Counter n n n Cyclic structure – Sequential depth is undefined. Circuit is

Modulo-3 Counter n n n Cyclic structure – Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9 Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 15

Adding Initializing Hardware Initializable modulo-3 counter CNT F 2 F 1 s-a-0 Z s-a-1

Adding Initializing Hardware Initializable modulo-3 counter CNT F 2 F 1 s-a-0 Z s-a-1 CLR s-a-1 Untestable fault Potentially detectable faults s - graph F 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt F 2 16

Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults

Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) Copyright 2001, Agrawal & Bushnell s 1196 14 14 18 529 Cycle-free 4 1242 1239 0 3 0 99. 8 100. 0 3 313 10 s 1238 14 14 18 508 Cycle-free 4 1355 1283 0 72 0 94. 7 100. 0 3 308 15 VLSI Test: Lecture 13/12 alt s 1488 8 19 6 653 Cyclic -1486 1384 2 26 76 93. 1 94. 8 24 525 19941 s 1494 8 19 6 647 Cyclic -1506 1379 2 30 97 91. 6 93. 4 28 559 19183 17

Asynchronous Circuit n n n An asynchronous circuit contains unclocked memory often realized by

Asynchronous Circuit n n n An asynchronous circuit contains unclocked memory often realized by combinational feedback. Almost impossible to build, let alone test, a large asynchronous circuit. Clock generators, signal synchronizers, flip-flops are typical asynchronous circuits. Many large synchronous systems contain small portions of localized asynchronous circuitry. Sequential circuit ATPG should be able to generate tests for circuits with limited asynchronous parts, even if it does not detect faults in those parts. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 18

Asynchronous Model Synchronous PIs CK PPI CK Feedback-free Combinational Logic C PPO Synchronous POs

Asynchronous Model Synchronous PIs CK PPI CK Feedback-free Combinational Logic C PPO Synchronous POs System Clock, CK Clocked Flip-flops Fast model Clock, FMCK Feedback delays Copyright 2001, Agrawal & Bushnell Combinational Feedback Paths: Feedback set VLSI Test: Lecture 13/12 alt Modeling circuit is Shown in orange. 19

Time-Frame Expansion Vector k PI Feedback set PPI C CK PO Time-frame -k+1 Copyright

Time-Frame Expansion Vector k PI Feedback set PPI C CK PO Time-frame -k+1 Copyright 2001, Agrawal & Bushnell C FMCK Feedback set PPO Asynchronous feedback stabilization Time-frame k VLSI Test: Lecture 13/12 alt Time-frame -k-1 20

Asynchronous Example 0 0 1 1 s-a-0 1 X 1 1 0 X 0

Asynchronous Example 0 0 1 1 s-a-0 1 X 1 1 0 X 0 0 1 1 s-a-0 1 0 Vectors 1 2 3 4 s-a-0 s-a-1 Outputs 1 2 3 4 Gentest results: Faults: total 23, detected 15, untestable 8 (shown in red), potentially detectable none Vectors: 4 Sparc 2 CPU time: test generation 33 ms, fault simulation 16 ms Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 21

Summary n Combinational ATPG algorithms are extended: § § § n Cycle-free circuits: §

Summary n Combinational ATPG algorithms are extended: § § § n Cycle-free circuits: § § n Require at most dseq + 1 time-frames Always initializable Cyclic circuits: § § § n Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time May need 9 Nff time-frames Circuit must be initializable Partial scan make circuit cycle-free (Chapter 14) Asynchronous circuits: § § § High complexity Low coverage and unreliable tests Simulation-based methods are more useful (Section 8. 3) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 22

Exercise n Which type of circuit is easier to test? Circle one in each:

Exercise n Which type of circuit is easier to test? Circle one in each: n n Combinational or sequential Cyclic or cycle-free Synchronous or asynchronous What is the maximum number of input vectors that may be needed to initialize a cycle-free circuit with k flip-flops? Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 23

Answers to Exercise n Which type of circuit is easier to test? Circle one

Answers to Exercise n Which type of circuit is easier to test? Circle one in each: n n Combinational or sequential Cyclic or cycle-free Synchronous or asynchronous What is the maximum number of input vectors that may be needed to initialize a cycle-free circuit with k flip-flops? k vectors. Because that is the maximum sequential depth possible. An example is a k bit shift register. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 13/12 alt 24

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