Lecture 13 n Overview of sequential logic Basic

Lecture 13 n Overview of sequential logic ¡ ¡ Basic concepts An example 1

Sequential vs. combinational n Combinational systems are memoryless ¡ Outputs depend only on the present inputs Inputs n System Outputs Sequential systems have memory ¡ Outputs depend on the present and the previous inputs Inputs System Outputs 2 Feedback

Sequential vs. combinational A C B clock Apply fixed inputs A, B When the clock ticks, the output becomes available Observe C Wait for another clock tick Observe C again Combinational: C will stay the same Sequential: C may be different 3

Synchronous sequential systems n Memory holds a system’s state ¡ ¡ Changes in state occur at specific times A periodic signal times or clocks the state changes 4

Clock A C B clock State changes occur at rising edge of clock pulsewidth clock period 5

Steady-state abstraction n The clock period must be long enough for all voltages to settle to a steady state before the next state change Clock hides transient behavior clock C Settled value 6

Recap: Sequential logic n Mostly has clock (for us, always) ¡ ¡ n Has state ¡ n n Synchronous = clocked Exception: Asynchronous circuits State = memory Employs feedback Assumes steady-state signals ¡ ¡ Signals are valid after they have settled State elements hold their settled output values 7

Example: Sequential system n Door combination lock ¡ ¡ n Inputs? ¡ n Sequence of numbers, reset, new Outputs? ¡ n Enter three numbers in sequence and the door opens As each new number is entered, press ‘new’ (like ‘enter) If there is an error the lock must be reset After the door opens the lock must be reset Door open/close Memory? ¡ Must remember the combination and what was entered 8

Understand the problem n n How many bits per input? How many inputs in sequence? How do we know a new input is entered? How do we represent the system states? clock ¡ new value reset What are the system states? open/closed 9

Implementation n A diagram may be helpful ¡ ¡ Assume synchronous inputs State sequence n n ¡ Enter 3 numbers serially Remember if error occurred All states have outputs n Lock open or closed 10

Finite-state diagram n States: 5 ¡ n n Each state has outputs Outputs: open/closed Inputs: reset, new, results of comparisons ¡ Assume synchronous inputs We use state diagrams to represent sequential logic System transitions between finite numbers of states 11

Finite-state diagram ERR closed C 1!= value & new S 1 reset closed C 1== value & new Shorthand: implies arrow from every state not new labeled ‘reset’ S 2 closed C 2!= value & new S 3 C 2== value & new not new closed C 3!= value & new C 3== value & new OPEN open not new 12

Separate data path and control n Data path ¡ ¡ n Stores combination Compares inputs with combination C 1 4 C 2 4 C 3 4 multiplexer 4 comparator ¡ ¡ State-machine controller State changes clocked new reset mux control 4 value Control controller clock equal open/closed 13

Refine state diagram n Refine state diagram to include internal structure ERR closed not equal & new reset S 1 closed mux=C 1 equal & new not equal & new S 2 S 3 OPEN closed open mux=C 2 equal mux=C 3 equal & new not new 14

Generate state table reset 1 0 0 0. . . new – 0 1 1 equal – – 0 1 state – S 1 S 1 next state S 1 ERR S 2 1 1 S 3 OPEN – mux C 1 – C 2 open/closed closed open 15

Encode state table n State can be: S 1, S 2, S 3, OPEN, or ERR ¡ ¡ ¡ n Output to mux can be: C 1, C 2, or C 3 ¡ ¡ n Need at least 3 bits to encode: 000, 001, 010, 011, 100 Can use 5 bits: 00001, 00010, 00100, 01000, 10000 Choose 4 bits: 0001, 0010, 0100, 1000, 0000 Need 2 or 3 bits to encode Choose 3 bits: 001, 010, 100 Output open/closed can be: Open or closed ¡ ¡ Need 1 or 2 bits to encode Choose 1 bit: 1, 0 16

Encode state table n Good encoding choice! ¡ ¡ ¡ Mux control is identical to last 3 state bits Open/closed is identical to first state bit Output encoding the outputs and state bits are the same reset 1 0 0 0. . . next state 0001 0000 0010 new – 0 1 1 equal – – 0 1 state – 0001 mux 001 – 010 1 1 0100 1000 – open/closed 0 0 1 17

Implementing the controller n special circuit element, called a register, for storing inputs when told to by the clock Will learn how to design the controller given the encoded state-transition table new mux control equal reset comb. logic state clock open/closed 18

Designing the datapath C 1 4 C 2 4 C 3 4 multiplexer mux control 4 value 4 comparator equal 19

Designing the datapath n Four multiplexers ¡ n C 2 i C 3 i mux control 2 -input ANDs and 3 input OR Four single-bit comparators ¡ n valuei C 1 i 2 -input XNORs 4 -input AND equal 20

Where did we use memory? n Memory: Stored combination, state (errors or successes in past inputs) new equal reset value C 1 C 2 C 3 multiplexer mux controller comparator equal clock open/closed 21

Where did we use feedback? n Feedback: Comparator output ("equal" signal) new equal reset value C 1 C 2 C 3 multiplexer mux controller clock comparator equal open/closed 22

Where did we use clock? n Clock synchronizes the inputs ¡ n Accept inputs when clock goes high Controller is clocked ¡ Mux-control and open/closed signals change on the clock edge new equal reset value C 1 C 2 C 3 multiplexer mux controller clock comparator equal open/closed 23