Lecture 12 Principles of Computer Operations What Computers


























![Instruction Fetch (IF) • Instr = MEM[PC] – PC is 2200 – Control Unit Instruction Fetch (IF) • Instr = MEM[PC] – PC is 2200 – Control Unit](https://slidetodoc.com/presentation_image_h2/d6eb54d68f477681a6bd508bed2bd205/image-27.jpg)



![Data Fetch (DF) • Read data from memory – SRC 1 = MEM[SRC_ADDR 1] Data Fetch (DF) • Read data from memory – SRC 1 = MEM[SRC_ADDR 1]](https://slidetodoc.com/presentation_image_h2/d6eb54d68f477681a6bd508bed2bd205/image-31.jpg)



![Write Result (WR) • Writes result to memory • MEM[DST_ADDR] = RES • Cycle Write Result (WR) • Writes result to memory • MEM[DST_ADDR] = RES • Cycle](https://slidetodoc.com/presentation_image_h2/d6eb54d68f477681a6bd508bed2bd205/image-35.jpg)

- Slides: 36
Lecture 12 Principles of Computer Operations
What Computers Can and Cannot Do • Computers deterministically perform instructions • No creativity, intuition, etc.
The Fetch/Execute Cycle • “Instruction Execution Engine” • Fetch/Execute Cycle – Fetch next instruction – Decode – Gather needed data – Perform op – Save result – Repeat
A Five-Step Cycle • Ops repeat forever
Anatomy of a Computer • All computers have 1. Memory, 2. Control unit, 3. Arithmetic/logic unit (ALU), 4. Input unit, and 5. Output unit
Principal Subsystems of a Computer
1. Memory • Memory – Code and data – Sequence of cells to hold bytes
1. Memory • Addresses – 0 to 232 – 1 (32 -bit CPU) • Values – 8 -bit • Finite capacity
Byte-Size Memory Location • Discrete locations are shown as 1 B boxes
Byte-Size Memory Location • Location can store 8 -bits – ASCII character – Number (how big? ) • Block of four bytes is word
Random Access Memory • Random access memory (RAM) – Order and time of access – Measured in MB or GB
2. Control Unit • Control unit – Circuitry handles Fetch/Execute Cycle • Typical machine instruction ADD 4000, 2080
2. Control Unit • ADD 4000, 2080 – Sums all three #s? – OP Dest, Src 1, Src 2
Illustration of a single instruction
3. Arithmetic/Logic Unit (ALU) • ALU does math – Uses logic gates (AND, OR, NOT) – +, -, *, /, etc.
4. And 5. Input and Output Units • Input – Info => computer • Output – Info => User • Useless without
The Peripherals • Peripherals connect to I/O ports • Not considered part of computer • Encode or decode info b/w computer and physical world
The Peripherals • Keyboard – Encodes keystrokes • Monitor – Decodes memory • Peripherals handle physical part of operation
Portable Memory & Hard Drives • Storage peripherals can do both I/O – USB memory – Hard disks/drives
Hard Disk • Hard disk stores programs and data – Large capacity relative to RAM – Slow relative to RAM • Programs/data must reside in RAM for use
A Device Driver for Every Peripheral • Most peripheral devices are “dumb” – Need drivers – Video card, monitor – Printer – Mouse, keyboard
The Program Counter: The PC's PC • Program counter (PC) • Maintains address of next instr. • Instr Fetch (IF) – Instr. = MEM[PC] – PC = PC + 4
Branch and Jump Instructions • Next instr. may not come after previous • Instr. may change PC – Jump – Branch
Instruction Interpretation • Process of executing a program is instruction interpretation • Our language => computer language
The Fetch/Execute Cycle • A five-step cycle: 1. Instruction Fetch (IF) 2. Instruction Decode (ID) 3. Data Fetch (DF) / Operand Fetch (OF) 4. Instruction Execution (EX) 5. Result Return (RR) / Write Result (WR) / Store (ST)
ADD 800, 428, 884
Instruction Fetch (IF) • Instr = MEM[PC] – PC is 2200 – Control Unit (CU) holds instr. • Bits of instr are decoded • PC updated
IF ADD 800, 428, 884
Instruction Decode (ID) • Decoder – Determines op to perform • Sets up ALU – Determines operand addresses • Sources • Destination • Passes to data fetch stage
ID + ADD 800 428 884
Data Fetch (DF) • Read data from memory – SRC 1 = MEM[SRC_ADDR 1] – SRC 2 = MEM[SRC_ADDR 2]
DF 42 12
Instruction Execution (EX) • Performs op indicated by ID – RES = SRC 1 OP SRC 2 – Result held in ALU
EX 54
Write Result (WR) • Writes result to memory • MEM[DST_ADDR] = RES • Cycle begins again
RR 54