Lecture 10 Registers Counters and Shifters Prith Banerjee

Lecture 10 Registers, Counters and Shifters Prith Banerjee ECE C 03 Advanced Digital Design Spring 1998 ECE C 03 Lecture 10 1

Outline • • • Registers Register Files Counters Designs of Counters with various FFs Shifters READING: Katz 7. 1, 7. 2, 7. 4, 7. 5, 4. 7 Dewey 10. 2, 10. 3, 10. 4, Hennessy-Patterson B 26 ECE C 03 Lecture 10 2

Building Complex Memory Elements • Flipflops: most primitive "packaged" sequential circuits • More complex sequential building blocks: Storage registers, Shift registers, Counters Available as components in the TTL Catalog • How to represent and design simple sequential circuits: counters • Problems and pitfalls when working with counters: Start-up States Asynchronous vs. Synchronous logic ECE C 03 Lecture 10 3

Registers • Storage unit. Can hold an n-bit value • Composed of a group of n flip-flops – Each flip-flop stores 1 bit of information • Normally use D flip-flops D Q Dff clk C 03 Lecture 10 ECE 4

Controlled Register D Q Dff clk ECE C 03 Lecture 10 5

Registers Group of storage elements read/written as a unit 4 -bit register constructed from 4 D FFs Shared clock and clear lines Schematic Shape TTL 74171 Quad D-type FF with Clear (Small numbers represent pin #s on package) ECE C 03 Lecture 10 6

Variations of Registers Selective Load Capability Tri-state or Open Collector Outputs True and Complementary Outputs 74377 Octal D-type FFs with input enable EN enabled low and lo-to-hi clock transition to load new data into register 74374 Octal D-type FFs with output enable OE asserted low presents FF state to output pins; otherwise high impedence ECE C 03 Lecture 10 7

Register Files Two dimensional array of flipflops Address used as index to a particular word Word contents read or written Separate Read and Write Enables Separate Read and Write Address Data Input, Q Outputs Contains 16 D-ffs, organized as four rows (words) of four elements (bits) 74670 4 x 4 Register File with Tri-state Outputs ECE C 03 Lecture 10 8

Shift Registers Storage + ability to circulate data among storage elements Reset Shift Direction J Q K Q Shift Reset Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Q 1 Q 2 Q 3 Q 4 Wrap around from rightmost element to leftmost element Master Slave FFs: sample inputs while clock is high; change outputs on falling edge ECE C 03 Lecture 10 9

Shift Registers I/O Serial vs. Parallel Inputs Serial vs. Parallel Outputs Shift Direction: Left vs. Right QD QC QB QA 74194 4 -bit Universal Shift Register Serial Inputs: LSI, RSI Parallel Inputs: D, C, B, A Parallel Outputs: QD, QC, QB, QA Clear Signal Positive Edge Triggered Devices S 1, S 0 determine the shift function S 1 = 1, S 0 = 1: Load on rising clk edge synchronous load S 1 = 1, S 0 = 0: shift left on rising clk edge LSI replaces element D S 1 = 0, S 0 = 1: shift right on rising clk edge RSI replaces element A S 1 = 0, S 0 = 0: hold state Multiplexing logic on input to each FF! Shifters well suited for serial-to-parallel conversions, ECE C 03 Lecture 10 such as terminal to computer communications 10

Application of Shift Registers Parallel to Serial Conversion D 7 D 6 D 5 D 4 Clock Parallel Inputs D 3 D 2 D 1 D 0 Sender Receiver S 1 S 0 194 LSI D QD C QC B QB A QA RSI CLK CLR D 7 D 6 D 5 D 4 S 1 S 0 194 LSI D QD C QC B QB A QA RSI CLK CLR D 3 D 2 D 1 D 0 Parallel Outputs Serial transmission ECE C 03 Lecture 10 11

Counters Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, . . . 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, . . . Binary vs. BCD vs. Gray Code Counters A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output ECE C 03 Lecture 10 12

Johnson Counters + 1 0 + + Reset S J Q CLK K Q R Q 1 S J Q CLK K Q R Q 2 S J Q CLK K Q R Q 3 S J Q CLK K Q R End-Around Q 4 Shift + 100 Shift Q 1 1 1 0 0 Q 2 0 1 1 0 0 0 Q 3 0 0 1 1 0 0 Q 4 0 0 0 1 1 0 8 possible states, single bit change per state, useful for avoiding glitches ECE C 03 Lecture 10 13

Catalog Counters 7 P 10 T 163 15 2 CLK RCO 6 5 4 3 D C B A 9 LOAD 1 CLR QD QC QB QA 11 12 13 14 74163 Synchronous 4 -Bit Upcounter Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D, C, B, A P, T Enable Inputs: both must be asserted to enable counting RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output" 74161: similar in function, asynchronous load and reset ECE C 03 Lecture 10 14

74163 Detailed Timing Diagram CLR LOAD A B C D CLK P T QA QB QC QD RCO Clear 12 Load 13 14 15 0 1 ECE Count C 03 Lecture 10 2 Inhibit 15

Counter Design Procedure This procedure can be generalized to implement ANY finite state machine Counters are a very simple way to start: no decisions on what state to advance to next current state is the output Example: 3 -bit Binary Upcounter 00 0 0 01 Present State Next State Flipflop Inputs C B A C+ B+ A+ TC TB TA 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1 1 0 State Transition Table 1 0 1 0 0 0 0 1 0 1 0 1 1 1 1 1 Flipflop Input Table ECE C 03 Lecture 10 Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? This is called "Remapping the Next State Function" 16

Example Design of Counter K-maps for Toggle Inputs: A CB 00 11 01 Resulting Logic Circuit: 10 0 1 TA = A CB 00 01 11 10 0 1 TB = A CB 00 01 11 10 0 1 TC = ECE C 03 Lecture 10 17

Resultant Circuit for Counter K-maps for Toggle Inputs: Resulting Logic Circuit: + TSQ Reset CLK Q R QA T SQ CLK Q R QB QC T SQ CLK Q R Count Timing Diagram: ECE C 03 Lecture 10 18

More Complex Counter Design Step 1: Derive the State Transition Diagram Count sequence: 000, 011, 101, 110 Present State Next State Step 2: State Transition Table 000 011 101 110 0 0 1 1 0 1 0 0 1 1 0 0 ECE C 03 Lecture 10 19

Complex Counter Design (Contd) Step 1: Derive the State Transition Diagram Count sequence: 000, 011, 101, 110 Present State 000 001 010 011 100 101 110 111 Next State 0 1 0 XXX 0 1 1 1 0 1 XXX 1 1 0 0 XXX Step 2: State Transition Table Note the Don't Care conditions ECE C 03 Lecture 10 20

Counter Design (Contd) Step 3: K-Maps for Next State Functions A CB 00 01 11 10 A 0 0 1 1 C+ = CB 00 01 11 10 B+ = A CB 00 01 11 10 0 1 A+ = ECE C 03 Lecture 10 21

Counter Design (contd) Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions Present State Q Q+ T 0 0 1 1 0 0 1 Toggle Excitation Table CBA 000 001 010 011 100 101 110 111 Toggle Inputs TC TB TA 0 1 0 XXX 0 0 1 1 1 0 XXX 0 1 1 0 XXX Remapped Next State Functions ECE C 03 Lecture 10 22

Resultant Counter Design Remapped K-Maps A CB 00 01 11 10 A 0 0 1 1 CB 00 TC 01 11 10 TB A CB 00 01 11 10 0 1 TA TC = A C + A C = A xor C TB = A + B + C TA = A B C + B C ECE C 03 Lecture 10 23

Resultant Circuit for Complex Counter Resulting Logic: 5 Gates 13 Input Literals + Flipflop connections TC Count T S Q C TB CLK Q C R B T S Q CLK Q B R TA A T S Q CLK Q A R Reset A C Timing Waveform: A B C TC TB ECE C 03 Lecture 10 A B C B C TA 24

Implementing Counters with Different FFs • Different counters can be implemented best with different counters • Steps in building a counter – Build state diagram – Build state transition table – Build next state K-map • Implementing the next state function with different FFs • Toggle flip flops best for binary counters • Existing CAD software for finite state machines favor D FFs ECE C 03 Lecture 10 25

Implementing 5 -state counter with RS FFs Continuing with the 000, 011, 101, 110, 000, . . . counter example Q Q+ R S 0 0 1 1 0 1 X 0 1 0 X Q+ = S + R Q RS Exitation Table Present State 000 001 010 011 100 101 110 111 Next State 0 1 0 XXX 0 1 1 1 0 1 XXX 1 1 0 0 XXX Rmepped next state RC SC RB SB RA SA X X X 0 X 0 1 X 1 X X 0 X 1 0 X X 0 1 0 X X X 1 0 X X Remapped Next State Functions ECE C 03 Lecture 10 26

Implementation with RS FFs Continued A CB 00 01 11 X X 0 X 0 0 1 10 CB 00 01 11 10 0 0 X 1 X X A RC CB SC 00 01 11 10 0 1 X 1 X 0 A CB SC = A 00 01 11 10 0 1 X 0 X 1 A RB A 0 1 CB 00 01 X X 0 0 RA X X 10 X 1 A 0 1 CB RB = A B + B C SB = B RA = C SB 11 RC = A SA = B C 00 01 0 X 11 0 X ECE C 03 Lecture SA 10 10 X 0 27

Implementation With RS FFs A A R Q CLK Q S C RB R Q CLK Q S B C Count A C B B C SA R Q CLK Q S B RB A A B C SA Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections ECE C 03 Lecture 10 28

Implementing with JK FFs Continuing with the 000, 011, 101, 110, 000, . . . counter example Q Q+ J K 0 0 1 1 X X 1 0 0 1 0 1 X X Q+ = S + R Q RS Exitation Table Present State 000 001 010 011 100 101 110 111 Next Rmepped next state State JC KC JB KB JA KA 0 1 0 XXX 0 1 1 1 0 1 XXX 1 1 0 0 XXX 0 1 X X X X 1 X X 0 1 X X 1 X 0 X X X 1 X X 0 X X X 1 0 X X X Remapped Next State Functions ECE C 03 Lecture 10 29

Implementation with JK FFs A CB 00 01 11 10 A 0 0 1 1 CB 00 JC A CB 00 01 01 11 10 JC = A KC 11 10 A CB KC = A/ 00 01 11 10 0 0 JB = 1 1 1 KB = A + C JB A CB 00 01 11 10 A 0 0 1 1 JA JA = B C/ KB CB 00 01 11 KA = C 10 KA ECE C 03 Lecture 10 30

Implementation with JK FFs + A A J Q C CLK K Q KB C J Q B CLK K Q B JA C J Q A CLK K Q A Count A C KB B C JA Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections ECE C 03 Lecture 10 31

Implementation with D FFs Simplest Design Procedure: No remapping needed! DC = A DB = A C + B DA = B C Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections ECE C 03 Lecture 10 32

Comparison with Different FF Types • T FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example! • No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key • D FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the key ECE C 03 Lecture 10 33

Asynchronous vs. Synchronous Counters Deceptively attractive alternative to synchronous design style Ripple Counters T Q CLK Q Count A T Q CLK Q B T Q C CLK Q Count signal ripples from left to right Count Reset A B C State transitions are not sharp! Can lead to "spiked outputs" from combinational logic decoding the counter's state ECE C 03 Lecture 10 34

Power of Synchronous Clear and Load Starting Offset Counters: e. g. , 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . . D C B A R Q Q QQ C D CBA OC L P T K DCBA 1 6 3 + L O C A L D R + Load 0 1 0110 is the state to be loaded Use RCO signal to trigger Load of a new state Since 74163 Load is synchronous, state changes only on the next rising clock edge ECE C 03 Lecture 10 35

Shifters • We have discussed some core logic design circuits for designing datapaths of computers – adders – ALUs – multipliers • A final component which is very important is a shifter – Takes a n-bit input and performs a shift left or right by m bits – Can define arithmetic shifts, logical shifts or circular shifts, e. g. circular shift left a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ECE C 03 Lecture 10 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 7 36

8 -input Barrel Shifter Specification: Inputs: D 7, D 6, …, D 0 Outputs: O 7, O 6, …, O 0 Control: S 2, S 1, S 0 shift input the specified number of positions to the right Understand the problem: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 . . . O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 S 2, S 1, S 0 = 0 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 . . . O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 S 2, S 1, S 0 = 0 0 1 ECE C 03 Lecture 10 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 . . . O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 S 2, S 1, S 0 = 0 1 0 37

Functional Description of Shifter Function Table Boolean equations O 7 = S 2' S 1' S 0' D 7 + S 2' S 1' S 0 D 6 + … + S 2 S 1 S 0 D 0 O 6 = S 2' S 1' S 0' D 6 + S 2' S 1' S 0 D 5 + … + S 2 S 1 S 0 D 7 O 5 = S 2' S 1' S 0' D 5 + S 2' S 1' S 0 D 4 + … + S 2 S 1 S 0 D 6 O 4 = S 2' S 1' S 0' D 4 + S 2' S 1' S 0 D 3 + … + S 2 S 1 S 0 D 5 O 3 = S 2' S 1' S 0' D 3 + S 2' S 1' S 0 D 2 + … + S 2 S 1 S 0 D 4 O 2 = S 2' S 1' S 0' D 2 + S 2' S 1' S 0 D 1 + … + S 2 S 1 S 0 D 3 O 1 = S 2' S 1' S 0' D 1 + S 2' S 1' S 0 D 0 + … + S 2 S 1 S 0 D 2 10 S 1' S 0 D 7 + … + S 2 S 1 S 038 D 1 O 0 = S 2' S 1' ECE S 0' C 03 D 0 Lecture + S 2'

8 -input Barrel Shifter • Straightforward gate level implementation – Looking at the Boolean equations earlier it is not possible to simplify them • Discrete gate implementation would require – eight 4 -input AND gates and one 8 -input OR gate per outputfunction – total 64 8 -input AND gates, and 8 8 -input OR gates for 8 output functions – Requires 40 TTL SSI packages ECE C 03 Lecture 10 39

Alternative Implementations of Shifter • Use MSI components such as multiplexers and decoders • Each output function can be implemented by an 8: 1 multiplexer, need eight MUXex, eight packages • Use the control input S 2 S 1 S 0 to control mux D 7 D 6 … D 1 D 0 O 7 S 2 S 1 S 0 D 7 D 6 … D 1 D 0 O 6 S 2 S 1 S 0 ECE C 03 Lecture 10 D 7 D 6 … D 1 D 0 O 0 S 2 S 1 S 0 40

Shifter Design Using Switching Logic • Remember that one can use CMOS transistors as switches that turn on when the gate signal is high, and off when gate signal is low • Need 64 switches (transistors) plus a decoder in a regular design Crosspoint switches Fully Wired crosspoint switch ECE C 03 Lecture 10 41

Summary • • Registers Register Files Counters Designs of Counters with various FFs Shifters NEXT LECTURE: Memory Design READING: Katz 7. 6 ECE C 03 Lecture 10 42