Lecture 07 Static CMOS Logic CMOS Circuit Styles

Lecture 07: Static CMOS Logic

CMOS Circuit Styles q Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path l high noise margins - full rail to rail swing - VOH and VOL are at VDD and GND, respectively l l q low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes l l simpler, faster gates increased sensitivity to noise

Static Complementary CMOS q Pull-up network (PUN) and pull-down network (PDN) VDD PMOS transistors only … In 1 In 2 PUN In. N F(In 1, In 2, …In. N) … In 1 In 2 In. N pull-up: make a connection from VDD to F when F(In 1, In 2, …In. N) = 1 PDN pull-down: make a connection from F to GND when F(In 1, In 2, …In. N) = 0 NMOS transistors only PUN and PDN are dual logic networks

Threshold Drops VDD PUN VDD S D VDD 0 VDD VGS D S CL VDD 0 PDN VDD D S CL 0 VDD - VTn CL VGS VDD |VTp| S D CL

Construction of PDN q NMOS devices in series implement a NAND function A • B A B q NMOS devices in parallel implement a NOR function A+B A B

Dual PUN and PDN q PUN and PDN are dual networks l l De. Morgan’s theorems A+B=A • B [!(A + B) = !A • !B or !(A | B) = !A & !B] A • B=A+B [!(A • B) = !A + !B or !(A & B) = !A | !B] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN q Complementary gate is naturally inverting (NAND, NOR, AOI, OAI) q Number of transistors for an N-input logic gate is 2 N

CMOS NAND A B A • B A B A B F 0 0 1 1 1 0

CMOS NOR B A A+B A B A B F 0 0 1 0 1 0 0 1 1 0

Complex CMOS Gate B A C D OUT = !(D + A • (B + C)) A D B C

Standard Cell Layout Methodology Routing channel VDD signals GND What logic function is this?

OAI 21 Logic Graph X A j C C B X = !(C • (A + B)) C A PUN i i X B VDD j B A B C GND A PDN

Two Stick Layouts of !(C • (A + B)) A C B A B C VDD X X GND uninterrupted diffusion strip

Consistent Euler Path q An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph l Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C i X B VDD j GND q A A B C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)

OAI 22 Logic Graph A C B D X = !((A+B) • (C+D)) C D A B C VDD X B A B C D PUN A GND PDN

OAI 22 Layout A B D C VDD X GND q Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)

XNOR/XOR Implementation XNOR XOR A A A B B A B A B q How many transistors in each? q Can you create the stick transistor layout for the lower left circuit? A B

VTC is Data-Dependent 0. 5 /0. 25 NMOS 0. 75 /0. 25 PMOS A M 3 B M 4 F= A • B A D M 2 VGS 2 = VA –VDS 1 S D B M 1 VGS 1 = VB q weaker PUN Cint S The threshold voltage of M 2 is higher than M 1 due to the body effect ( ) VTn 1 = VTn 0 VTn 2 = VTn 0 + ( (|2 F| + Vint) - |2 F|) since VSB of M 2 is not zero (when VB = 0) due to the presence of Cint

Static CMOS Full Adder Circuit !Cout = !Cin & (!A | !B) | (!A & !B) !Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin) B A B B A Cin A B Cin !Cout A A B B A !Sum Cin A B Cout = Cin & (A | B) | (A & B) Sum = !Cout & (A | B | Cin) | (A & B & Cin)