LearningBased Approximation of Interconnect Delay and Slew Modeling

Learning-Based Approximation of Interconnect Delay and Slew Modeling in Signoff Timing Tools Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath and Jyoti Wadhwani VLSI CAD LABORATORY, UC San Diego 15 th ACM/IEEE System-Level Interconnect Prediction Workshop June 2 nd, 2013 UC San Diego / VLSI CAD Laboratory

Outline Motivation n Learning-based Interconnect Modeling n Correlation Methodology with Signoff Timer n Experimental Results n Conclusions and Future Works n -2 -

Motivation n Incremental static timing analysis (i. STA) is the backbone of post-layout design optimization – Using Signoff Timer Runtime increase – Using Internal Timer Less accuracy Post-Layout Optimizer An accurate internal timer is needed Gate Sizing/Vt-Swapping Internal Timer i. STA Iterative invocation Runtime increase Timing Discrepancy Signoff Timer i. STA Signoff -3 -

Motivation n Challenges in matching signoff timer – Error propagation along paths – Error accumulation with netlist changes Error accumulation with netlist change Error (internal timer – signoff timer) Error propagation on paths Error Our goal: minimize the error # cell change # logic depth along path Netlist change -4 -

Our Work n We minimize divergence ‘d’ between internal and signoff timers Two basic techniques – Learning-based modeling of wire delay and slew – Offset-based timing correlation Signoff Timer accuracy n d We achieve small divergence ‘d’ d Offset-based timing correlation Learning-based modeling Internal Timer runtime -5 -

Outline Motivation n Learning-based Interconnect Modeling n Correlation Methodology with Signoff Timer n Experimental Results n Conclusions and Future Works n -6 -

Preliminary: Delay and Slew n Delay : 50% of input transition to 50% of output transition Slew : 10% to 90% of transition n Gate delay and slew: little divergence between timers n – Lookup table-based method is used not in our scope n Wire delay and slew: challenging to match signoff timer – Wire delay and slew models in signoff timer are unknown 50% Delay Slew 10% 90% -7 -

Error Distribution of Analytical Models n Existing analytical models Wire slew Wire delay 80% Elmore (EM) [Elmore 98] EM/Ln. S: overestimate D 2 M/PERI: underestimate 80% Regression Hard cases D 2 M [Alpert 00] Hard cases cannot be estimated by any single model Hard cases Classification 80% PERI [Kashyap 02] 80% Lognormal Slew (Ln. S) [Alpert 03] Hard cases -8 -

Why Classification? Data points in each class have stronger linear fit between measured and estimated values after classification Measured values n Estimated values Measured values Estimated values -9 -

Classification Our “alpha” is chosen empirically n Alpha reflects degree of significance of ramp input on delay metric [Kashyap 02] n Wire slew Wire delay Model 2 Model 1 Model 3 Model 2 Model 1 -10 -

Learning-based Interconnect Modeling n Our methodology – Classification + Least-Squares Regression (LSQR) Collect training data Classification LSQR -11 -

Learning-based Interconnect Modeling n Exhaustive search for the best regressor(s) and classifier(s) – Increasing the number of regressors/classifiers improves the accuracy until a certain point Maximum absolute wire delay error 14 ps 2 16 ps 1 0% -12% 14 ps -30% 20 ps 0 1 15% 23 ps 2 -33% -8% The number of regressors The number of classifiers Experimental results with all testcases (ISPD-2013) Maximum absolute wire slew error 2 -11% -23% 73 ps 0 1 -36% 31. 5 ps -4. 5% -8% 36 ps 1 21 ps 3 -1. 5% 32 ps 46. 8 ps 33 ps -29% -0. 0% 2 46. 5 ps 3 The number of regressors -12 -

Learning-based Interconnect Modeling n Learning-based models for wire delay and slew Wire delay modeling Wire slew modeling -1. 72 2. 35 0. 96 -3. 44 2. 07 -1. 05 1. 27 1. 02 -2. 39 1. 59 -2. 72 1. 41 2. 50 -1. 88 1. 30 -13 -

Outline Motivation n Learning-based Interconnect Modeling n Correlation Methodology with Signoff Timer n Experimental Results n Conclusions and Future Works n -14 -

Static Timing Analysis n Timing slack is calculated by STA Calculate slew Calculate delay 3 /5 /2 Calculate AAT/RAT 4 /6 /2 Calculate slack AAT / RAT / slack = RAT - AAT 15/15 /0 5 /5 /0 n 6 /6/0 11/11/0 12/12 /0 Endpoint (primary output, input of FF) timing slack errors are reported for evaluation -15 -

Correlation with Signoff Timer n Use timing information from signoff timer to compensate the difference (error) between internal and signoff timer offset = signoff timer – internal timer Internal Timer Signoff Timer i. STA Request timing information n Previous work: [Moon 10] Endpoint slack offset-based correlation – Can match slack in critical paths – May not be accurate when critical paths change -16 -

Correlation with Signoff Timer n Offset is calculated at each STA stage Internal timer Calculate slew Calculate delay Calculate AAT/RAT Calculate slack Slew offset Delay offset AAT/RAT offset Slack offset Slew Delay AAT/RAT Slack Signoff timer offset = signoff timer – internal timer n Correlated timing (slew/delay/AAT/RAT/slack) = timing values from internal timer + offset -17 -

Correlation Method vs. Quality Maximum absolute endpoint slack error for each correlation method AAT/delay/AAT+slew/delay+slew correlations give 10 X more accuracy during netlist changes compared to slack correlation [Moon 10] n n Experimental results with fft testcase (ISPD-2013) (ps) SLK 180 AAT DELAY AAT_TRAN DLY_TRAN 160 14 140 slack correlation 120 12 10 10 X 80 8 60 6 40 4 20 2 0 0. 0% 10. 0% 20. 0% % of changed cells 30. 0% AAT, delay, AAT+slew, delay+slew correlation 0 0. 0% 5. 0% 10. 0% 15. 0% 20. 0% % of changed cells 25. 0% 30. 0% -18 -

Timer in Post-Layout Optimizer n Internal timer for a post-layout optimizer invoke signoff timer Correlate() Netlist change Offset i. STA() # cell change > N? no yes -19 -

Outline Motivation n Learning-based Interconnect Modeling n Correlation Methodology with Signoff Timer n Experimental Results n Conclusions and Future Works n -20 -

Experimental Environment n n Technology : Liberty from ISPD-2013 Gate Sizing Contest Testcases : ISPD-2013 testcases Benchmark n #cells #nets #PI #FFs pci_bridge 32 30603 30763 160 fft 32766 33792 matrix_mult edit_dist 3359 #pins #PO 87813 201 1026 1984 105355 1984 156440 159642 3202 2898 459946 1600 126665 129227 2562 5661 374606 12 Signoff tool : Prime. Time© F-2011. 06 -SP 3 -7 -21 -

Error between Internal and Signoff Timer n Maximum absolute endpoint slack error for all (delay, slew) pairs Correlation-based approach can improve accuracy n (delay: D 2 M, slew: ML) shows the best result n Testcase: fft (ISPD-2013) (ps) 300 (EM, PERI) (D 2 M, ML) (ML, S 2 M) (ML, PERI) (ML, ML) (ps) without correlation with correlation 30 25 200 20 15 100 with correlation 50 10 X 10 5 (delay: D 2 M, slew: ML) 0 0 0. 0% 10. 0% 20. 0% % of changed cells 30. 0% 5. 0% 10. 0% 15. 0% 20. 0% 25. 0% 30. 0% % of changed cells -22 -

Conclusions and Future Works n n n Learning-based methodology can improve accuracy for endpoint timing slack estimation AAT/delay/AAT+slew/delay+slew offset-based correlation methods can achieve 10 X accuracy improvement for timing slack estimation Future works – Enhance model robustness across different libraries and testcases – Minimize the overhead of correlation methodology with a given accuracy – Application: industry-strength gate sizing optimizers -23 -

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