LCD Display DIO 2 Board CPLD DIO 2

LCD Display DIO 2 Board CPLD

DIO 2 Board • CPLD Interface • LCD Display

DIO 2 circuit board block diagram

Top Level Design

buff 3. vhd library IEEE; use IEEE. STD_LOGIC_1164. all; en input output entity buff 3 is generic (width: positive); port( input : in STD_LOGIC_vector(width-1 downto 0); en : in STD_LOGIC; output : out STD_LOGIC_vector(width-1 downto 0) ); end buff 3; architecture buff 3 of buff 3 is begin output <= input when en = '1' else (others => 'Z'); end buff 3;

DIO 2 CPLD VHDL Code library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity d 2 io is Port ( btns : in std_logic_vector(14 downto 0); switchs : in std_logic_vector(7 downto 0); leds : out std_logic_vector(15 downto 0); data : inout std_logic_vector(7 downto 0); addr : in std_logic_vector(5 downto 0); sseg : out std_logic_vector(6 downto 0); ssegdp : out std_logic; ssegsel : out std_logic_vector(3 downto 0); cs : in std_logic; we : in std_logic; oe : in std_logic; clk 256 : in std_logic); end d 2 io;

architecture rtl of d 2 io is signal signal data_out : std_logic_vector(7 downto 0); sseg_reg : std_logic_vector(15 downto 0); digit : std_logic_vector(3 downto 0); count : unsigned(1 downto 0); leds_i : std_logic_vector(15 downto 0); signal strobe : std_logic; begin ssegdp <= '1'; data <= data_out when (oe = '1' and cs = '1') else (others => 'Z'); data_out <= btns(7 downto 0) when addr(1 downto 0) = "00" else '0'& btns(14 downto 8) when addr(1 downto 0) = "01" else switchs;

strobe <= cs and we; leds <= not(leds_i); process(strobe) begin if(falling_edge(strobe)) then case addr is when "000100" => leds_i(7 downto 0) <= data; when "000101" => leds_i(15 downto 8) <= data; when "000110" => sseg_reg(15 downto 8) <= data; when "000111" => sseg_reg(7 downto 0) <= data; when others => NULL; end case; end if; end process;

process(clk 256) begin if(rising_edge(clk 256)) then count <= count + 1; end if; end process; with count select digit <= sseg_reg(7 downto 4) when "00", sseg_reg(3 downto 0) when "01", sseg_reg(15 downto 12) when "10", sseg_reg(11 downto 8) when others; process(count) begin ssegsel <= (others => '0'); ssegsel(conv_integer(count)) <= '1'; end process;

with digit select sseg <= "1001111" "0010010" "0000110" "1001100" "0100000" "0001111" "0000000" "0000100" "0001000" "1100000" "0110001" "1000010" "0110000" "0111000" "0000001" end rtl; when when when when "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111", others; --1 --2 --3 --4 --5 --6 --7 --8 --9 --A --b --C --d --E --F --0

DIO 2 Board • CPLD Interface • LCD Display

DIO 2 circuit board block diagram

In wc 16_control add…. when LCDistore => LCD_RW <= '0'; LCD_RS <= '0'; pinc <= '0'; if ccycle < 7 then LCD_E <= '1'; else tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; end if; when LCDdstore => LCD_RW <= '0'; LCD_RS <= '1'; pinc <= '0'; if ccycle < 7 then LCD_E <= '1'; else tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; end if; LCDinst! ( data 0. . ) LCDdata! ( data 0. . )

Lcd 3. whp LCD for Digilab DIO 2 LCD 3. WHP HEX : 1 ms_Delay ( -- ) 30 D 1 FOR NEXT ; : 30 ms. Delay ( -- ) 1 E FOR 1 ms_Delay NEXT ; : hex 2 asc ( n -- asc ) 0 F AND mask upper nibble DUP 9 > if n > 9 IF 37 + add $37 ELSE 30 + else add $30 THEN ;

Lcd 3. whp : lcd. init ( -- ) 30 ms. delay 3 C 0 LCDinst! 2 x 40 display 1 ms_Delay 0 f 0 LCDinst! display on 1 ms_Delay 1 0 LCDinst! display clear 1 ms_Delay 6 0 LCDinst! entry cursor shift off 1 ms_Delay ;

Lcd 3. whp : hex>lcd ( hex -- ) HEX 2 ASC 0 LCDdata! 30 ms. delay; : u. lcd ( u -- ) DUP C RSHIFT hex>lcd DUP 8 RSHIFT hex>lcd DUP 4 RSHIFT hex>lcd ; display T on LCD

Lcd 3. whp : MAIN ( -- ) lcd. init BEGIN wait. B 4 S@ DUP DIG! DUP hex>lcd 8 LSHIFT wait. B 4 S@ OR DUP DIG! DUP hex>lcd wait. B 4 u. lcd AGAIN ; get high byte get low byte display on lcd